- 专利标题: High threshold voltage NMOS transistors for low power IC technology
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申请号: US12727312申请日: 2010-03-19
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公开(公告)号: US08969969B2公开(公告)日: 2015-03-03
- 发明人: Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
- 申请人: Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Whitham, Curtis, Christofferson & Cook, P.C.
- 代理商 Joseph P. Abate
- 主分类号: H01L27/092
- IPC分类号: H01L27/092 ; H01L21/8234 ; H01L21/8238
摘要:
Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
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