The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.