中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.036 seconds)

    SYSTEM AND TECHNIQUE FOR RASTERIZING CIRCUIT LAYOUT DATA
    5.
    发明申请
    SYSTEM AND TECHNIQUE FOR RASTERIZING CIRCUIT LAYOUT DATA 有权
    用于对电路布局数据进行放大的系统和技术

    公开(公告)号：US20160180005A1

    公开(公告)日：2016-06-23

    申请号：US14576388

    申请日：2014-12-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Pei-Yi Liu ,  Cheng-Chi Wu ,  Cheng-Hung Chen ,  Jyuh-Fuh Lin ,  Wen-Chuan Wang ,  Shy-Jay Lin

    IPC: G06F17/50

    CPC classification number: G03F7/70508 ,  G03F7/70291 ,  G03F7/70383 ,  H01J2237/31764

    Abstract: A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.

    Abstract translation: 提供了将设计形状转换为像素值的技术。 该技术可以用于控制在工件上执行的直写或其他平版印刷工艺。 在示例性实施例中，该方法包括在计算系统处接收指定具有多于四个顶点的特征的设计数据库。 计算系统还接收像素网格。 确定与特征相对应的一组矩形，并且计算系统基于矩形集合来确定由特征重叠的像素网格的像素的面积。 在一些这样的实施例中，基于与特征重叠的面积为像素确定平版印刷曝光强度，并且提供用于图案化工件的光刻曝光强度。

    Long-range lithographic dose correction
    6.
    发明授权
    Long-range lithographic dose correction 有权
    长程光刻剂量校正

    公开(公告)号：US08984452B2

    公开(公告)日：2015-03-17

    申请号：US13966013

    申请日：2013-08-13

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Cheng-Hung Chen ,  Shy-Jay Lin ,  Jaw-Jung Shin ,  Wen-Chuan Wang ,  Pei-Yi Liu ,  Burn Jeng Lin

    IPC: G06F17/50

    CPC classification number: G03F7/70558 ,  G03F7/70616

    Abstract: A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.

    Abstract translation: 公开了一种量化光刻邻近效应并确定光刻曝光剂量的方法。 在示例性实施例中，用于确定曝光剂量的方法包括接收包括旨在形成在工件上的多个特征的设计数据库。 定义设计数据库的目标区域，使得目标区域包括目标特征。 也定义了靠近目标区域的设计数据库的区域。 确定该区域的近似值，其中近似表示区域内的暴露区域。 基于该区域的近似来确定区域对目标特征的邻近效应。 基于所确定的区域对目标特征的邻近效应来确定目标特征的总接近效应。

    Data process for E-beam lithography
    7.
    发明授权
    Data process for E-beam lithography 有权
    电子束光刻数据处理

    公开(公告)号：US08877410B2

    公开(公告)日：2014-11-04

    申请号：US14043264

    申请日：2013-10-01

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Cheng-Hung Chen ,  Pei-Shiang Chen ,  Shih-Chi Wang ,  Jeng-Horng Chen

    IPC: G03F1/20 ,  G06F17/50 ,  G03C5/00

    CPC classification number: G06F17/50 ,  G03C5/00 ,  G03F1/20 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01J2237/31769 ,  Y10S430/143

    Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

    Abstract translation: 本公开提供了通过电子束光刻系统增加晶片生产量的抖动方法。 抖动方法从顶点图生成边缘图。 顶点图是从集成电路设计布局（如原始图案位图）生成的。 也从集成电路设计布局生成灰色地图（也称为图案灰度图）。 通过将边缘图与灰度图组合，生成修改后的集成电路设计布局（修改图案位图），供电子束光刻系统使用。

    Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity
    9.
    发明授权
    Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity 有权
    制造具有块模块的集成电路的优化图案密度均匀性的方法

    公开(公告)号：US09436788B2

    公开(公告)日：2016-09-06

    申请号：US14253282

    申请日：2014-04-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jyuh-Fuh Lin ,  Pei-Yi Liu ,  Cheng-Hung Chen ,  Wen-Chuan Wang ,  Shy-Jay Lin ,  Burn Jeng Lin

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G03F1/36 ,  G06F17/5009 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  Y02P90/265

    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.

    Abstract translation: 本公开提供了IC方法的一个实施例，其包括接收包括多个主要特征的IC设计布局; 选择与IC设计布局的隔离距离; 根据每个隔离距离来调整主要特征; 根据超大的主要特征，通过布尔运算生成每个隔离距离的空间块层; 根据图案密度变化选择优化的空间块层和IC设计布局的优化块虚拟密度比; 根据优化的块模拟密度比，在优化的空间块层中产生虚拟特征; 以及形成包括主要特征和虚拟特征的IC设计布局的输出数据，用于IC制造。

    Method for image dithering for lithographic processes
    10.
    发明授权
    Method for image dithering for lithographic processes 有权
    光刻工艺图像抖动方法

    公开(公告)号：US09147377B2

    公开(公告)日：2015-09-29

    申请号：US13956267

    申请日：2013-07-31

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Cheng-Hung Chen ,  Shy-Jay Shin ,  Jaw-Jung Shin ,  Burn Jeng Lin

    IPC: G09G5/02

    CPC classification number: G09G5/02 ,  G03F7/70383 ,  G03F7/70558 ,  G06F7/70 ,  H01J37/00 ,  H01J37/3174 ,  H01J37/3178

    Abstract: The present disclosure provides a method for image dithering. The method includes providing a polygon related to an integrated circuit (IC) layout design in a graphic database system (GDS) grid; converting the polygon to an intensity map in the GDS grid, the intensity map including a group of partial pixels and a group of full pixels; performing a first quantization process to a partial pixel to determine a first error; applying the first error to one or more full pixels; performing a second quantization process to a full pixel to determine a second error; and distributing the second error to one or more full pixels. The partial pixels correspond to pixels partially covered by the polygon, and the full pixels correspond to pixels fully covered by the polygon.

    Abstract translation: 本公开提供了一种用于图像抖动的方法。 该方法包括在图形数据库系统（GDS）网格中提供与集成电路（IC）布局设计有关的多边形; 将所述多边形转换成所述GDS网格中的强度图，所述强度图包括一组部分像素和一组全像素; 对部分像素执行第一量化处理以确定第一误差; 将第一误差应用于一个或多个完整像素; 对全像素执行第二量化处理以确定第二误差; 并将第二个错误分配给一个或多个完整像素。 部分像素对应于由多边形部分地覆盖的像素，并且全像素对应于由多边形完全覆盖的像素。

Patent Agency Ranking