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    SYSTEM AND TECHNIQUE FOR RASTERIZING CIRCUIT LAYOUT DATA
    5.
    发明申请
    SYSTEM AND TECHNIQUE FOR RASTERIZING CIRCUIT LAYOUT DATA 有权
    用于对电路布局数据进行放大的系统和技术

    公开(公告)号：US20160180005A1

    公开(公告)日：2016-06-23

    申请号：US14576388

    申请日：2014-12-19

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Pei-Yi Liu ,  Cheng-Chi Wu ,  Cheng-Hung Chen ,  Jyuh-Fuh Lin ,  Wen-Chuan Wang ,  Shy-Jay Lin

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70508 ,  G03F7/70291 ,  G03F7/70383 ,  H01J2237/31764

    摘要： A technique for converting design shapes into pixel values is provided. The technique may be used to control a direct-write or other lithographic process performed on a workpiece. In an exemplary embodiment, the method includes receiving, at a computing system, a design database specifying a feature having more than four vertices. The computing system also receives a pixel grid. A set of rectangles corresponding to the feature is determined, and the computing system determines an area of a pixel of the pixel grid overlapped by the feature based on the set of rectangles. In some such embodiments, a lithographic exposure intensity is determined for the pixel based on the area overlapped by the feature, and the lithographic exposure intensity is provided for patterning of a workpiece.

    摘要翻译： 提供了将设计形状转换为像素值的技术。 该技术可以用于控制在工件上执行的直写或其他平版印刷工艺。 在示例性实施例中，该方法包括在计算系统处接收指定具有多于四个顶点的特征的设计数据库。 计算系统还接收像素网格。 确定与特征相对应的一组矩形，并且计算系统基于矩形集合来确定由特征重叠的像素网格的像素的面积。 在一些这样的实施例中，基于与特征重叠的面积为像素确定平版印刷曝光强度，并且提供用于图案化工件的光刻曝光强度。

    Long-range lithographic dose correction
    6.
    发明授权
    Long-range lithographic dose correction 有权
    长程光刻剂量校正

    公开(公告)号：US08984452B2

    公开(公告)日：2015-03-17

    申请号：US13966013

    申请日：2013-08-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Cheng-Hung Chen ,  Shy-Jay Lin ,  Jaw-Jung Shin ,  Wen-Chuan Wang ,  Pei-Yi Liu ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70558 ,  G03F7/70616

    摘要： A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.

    摘要翻译： 公开了一种量化光刻邻近效应并确定光刻曝光剂量的方法。 在示例性实施例中，用于确定曝光剂量的方法包括接收包括旨在形成在工件上的多个特征的设计数据库。 定义设计数据库的目标区域，使得目标区域包括目标特征。 也定义了靠近目标区域的设计数据库的区域。 确定该区域的近似值，其中近似表示区域内的暴露区域。 基于该区域的近似来确定区域对目标特征的邻近效应。 基于所确定的区域对目标特征的邻近效应来确定目标特征的总接近效应。

    Data process for E-beam lithography
    7.
    发明授权
    Data process for E-beam lithography 有权
    电子束光刻数据处理

    公开(公告)号：US08877410B2

    公开(公告)日：2014-11-04

    申请号：US14043264

    申请日：2013-10-01

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Cheng-Hung Chen ,  Pei-Shiang Chen ,  Shih-Chi Wang ,  Jeng-Horng Chen

    IPC分类号： G03F1/20 ,  G06F17/50 ,  G03C5/00

    CPC分类号： G06F17/50 ,  G03C5/00 ,  G03F1/20 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01J2237/31769 ,  Y10S430/143

    摘要： The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

    摘要翻译： 本公开提供了通过电子束光刻系统增加晶片生产量的抖动方法。 抖动方法从顶点图生成边缘图。 顶点图是从集成电路设计布局（如原始图案位图）生成的。 也从集成电路设计布局生成灰色地图（也称为图案灰度图）。 通过将边缘图与灰度图组合，生成修改后的集成电路设计布局（修改图案位图），供电子束光刻系统使用。

    Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity
    9.
    发明申请
    Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity 有权
    制造具有优化图案密度均匀性的集成电路的方法

    公开(公告)号：US20150294056A1

    公开(公告)日：2015-10-15

    申请号：US14252464

    申请日：2014-04-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jyuh-Fuh Lin ,  Pei-Yi Liu ,  Cheng-Hung Chen ,  Wen-Chuan Wang ,  Shy-Jay Lin ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36 ,  G06F17/5009 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  Y02P90/265

    摘要： The present disclosure provides an IC method that includes receiving an IC design layout having main features; generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks; calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout; calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space layers according to the main pattern density and the dummy pattern density; choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR; generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and forming a tape-out data of the modified IC design layout for IC fabrication.

    摘要翻译： 本公开提供一种IC方法，包括接收具有主要特征的IC设计布局; 向所述IC设计布局生成多个空间块层，每个所述空间块层与隔离距离和多个空间块相关联; 计算IC设计布局的主图案密度PD0和虚设图案密度PD; 根据主图案密度和虚拟图案密度计算每个空间层的IC设计布局的最小变化块虚拟密度比（LVBDDR）; 根据LVBDDR选择优化的空间块层和优化的块虚拟密度比; 根据优化的空间块层和优化的块虚拟密度比，从IC设计布局生成修改的IC设计布局; 并形成用于IC制造的改进的IC设计布局的输出数据。

    Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy
    10.
    发明申请
    Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy 有权
    具有改进临界尺寸精度的电子束接近校正方法

    公开(公告)号：US20150040079A1

    公开(公告)日：2015-02-05

    申请号：US13954635

    申请日：2013-07-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Cheng-Hung Chen ,  Jaw-Jung Shin ,  Shy-Jay Lin ,  Wen-Chuan Wang ,  Pei-Yi Liu ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G03F1/78 ,  H01J37/3026 ,  H01J2237/31764 ,  H01J2237/31771

    摘要： The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.

    摘要翻译： 本公开提供了集成电路（IC）方法的一个实施例。 该方法包括接收具有特征的IC设计布局; 将特征压裂成包括第一多边形的多个多边形; 将目标点分配给第一多边形的边缘; 计算第一多边形的校正曝光剂量，其中通过模拟基于目标点中的相应一个确定每个正确的曝光剂量; 基于所述校正的曝光剂量确定所述第一多边形的多边形曝光剂量; 以及准备用于光刻图案化的输出数据，其中所述输出数据定义所述多个多边形以及与所述多个多边形配对的多个多边形曝光剂量。