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    Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity
    3.
    发明授权
    Method of fabricating an integrated circuit with block dummy for optimized pattern density uniformity 有权
    制造具有块模块的集成电路的优化图案密度均匀性的方法

    公开(公告)号：US09436788B2

    公开(公告)日：2016-09-06

    申请号：US14253282

    申请日：2014-04-15

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jyuh-Fuh Lin ,  Pei-Yi Liu ,  Cheng-Hung Chen ,  Wen-Chuan Wang ,  Shy-Jay Lin ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36 ,  G06F17/5009 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  Y02P90/265

    摘要： The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a plurality of main features; choosing isolation distances to the IC design layout; oversizing the main features according to each of the isolation distances; generating a space block layer for the each of the isolation distances by a Boolean operation according to oversized main features; choosing an optimized space block layer and an optimized block dummy density ratio of the IC design layout according to pattern density variation; generating dummy features in the optimized space block layer according to the optimized block dummy density ratio; and forming a tape-out data of the IC design layout including the main features and the dummy features, for IC fabrication.

    摘要翻译： 本公开提供了IC方法的一个实施例，其包括接收包括多个主要特征的IC设计布局; 选择与IC设计布局的隔离距离; 根据每个隔离距离来调整主要特征; 根据超大的主要特征，通过布尔运算生成每个隔离距离的空间块层; 根据图案密度变化选择优化的空间块层和IC设计布局的优化块虚拟密度比; 根据优化的块模拟密度比，在优化的空间块层中产生虚拟特征; 以及形成包括主要特征和虚拟特征的IC设计布局的输出数据，用于IC制造。

    LONG-RANGE LITHOGRAPHIC DOSE CORRECTION
    4.
    发明申请
    LONG-RANGE LITHOGRAPHIC DOSE CORRECTION 有权
    LONGRANGE LITHOGRAPHIC DOSE CORLECTION

    公开(公告)号：US20150052489A1

    公开(公告)日：2015-02-19

    申请号：US13966013

    申请日：2013-08-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Cheng-Hung Chen ,  Shy-Jay Lin ,  Jaw-Jung Shin ,  Wen-Chuan Wang ,  Pei-Yi Liu ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70558 ,  G03F7/70616

    摘要： A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.

    摘要翻译： 公开了一种量化光刻邻近效应并确定光刻曝光剂量的方法。 在示例性实施例中，用于确定曝光剂量的方法包括接收包括旨在形成在工件上的多个特征的设计数据库。 定义设计数据库的目标区域，使得目标区域包括目标特征。 也定义了靠近目标区域的设计数据库的区域。 确定该区域的近似值，其中近似表示区域内的暴露区域。 基于该区域的近似来确定区域对目标特征的邻近效应。 基于所确定的区域对目标特征的邻近效应来确定目标特征的总接近效应。

    Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity
    6.
    发明申请
    Method of Fabricating an Integrated Circuit with Optimized Pattern Density Uniformity 有权
    制造具有优化图案密度均匀性的集成电路的方法

    公开(公告)号：US20150294056A1

    公开(公告)日：2015-10-15

    申请号：US14252464

    申请日：2014-04-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Jyuh-Fuh Lin ,  Pei-Yi Liu ,  Cheng-Hung Chen ,  Wen-Chuan Wang ,  Shy-Jay Lin ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36 ,  G06F17/5009 ,  G06F17/5081 ,  G06F2217/12 ,  H01L27/0207 ,  Y02P90/265

    摘要： The present disclosure provides an IC method that includes receiving an IC design layout having main features; generating a plurality of space block layers to the IC design layout, each of the space block layers being associated with an isolation distance and a plurality of space blocks; calculating main pattern density PD0 and dummy pattern density PDs of the IC design layout; calculating a least variation block dummy density ratio (LVBDDR) of the IC design layout for each of the space layers according to the main pattern density and the dummy pattern density; choosing an optimized space block layer and an optimized block dummy density ratio according to the LVBDDR; generating a modified IC design layout from the IC design layout according to the optimized space block layer and the optimized block dummy density ratio; and forming a tape-out data of the modified IC design layout for IC fabrication.

    摘要翻译： 本公开提供一种IC方法，包括接收具有主要特征的IC设计布局; 向所述IC设计布局生成多个空间块层，每个所述空间块层与隔离距离和多个空间块相关联; 计算IC设计布局的主图案密度PD0和虚设图案密度PD; 根据主图案密度和虚拟图案密度计算每个空间层的IC设计布局的最小变化块虚拟密度比（LVBDDR）; 根据LVBDDR选择优化的空间块层和优化的块虚拟密度比; 根据优化的空间块层和优化的块虚拟密度比，从IC设计布局生成修改的IC设计布局; 并形成用于IC制造的改进的IC设计布局的输出数据。

    Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy
    7.
    发明申请
    Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy 有权
    具有改进临界尺寸精度的电子束接近校正方法

    公开(公告)号：US20150040079A1

    公开(公告)日：2015-02-05

    申请号：US13954635

    申请日：2013-07-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Cheng-Hung Chen ,  Jaw-Jung Shin ,  Shy-Jay Lin ,  Wen-Chuan Wang ,  Pei-Yi Liu ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G03F1/78 ,  H01J37/3026 ,  H01J2237/31764 ,  H01J2237/31771

    摘要： The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.

    摘要翻译： 本公开提供了集成电路（IC）方法的一个实施例。 该方法包括接收具有特征的IC设计布局; 将特征压裂成包括第一多边形的多个多边形; 将目标点分配给第一多边形的边缘; 计算第一多边形的校正曝光剂量，其中通过模拟基于目标点中的相应一个确定每个正确的曝光剂量; 基于所述校正的曝光剂量确定所述第一多边形的多边形曝光剂量; 以及准备用于光刻图案化的输出数据，其中所述输出数据定义所述多个多边形以及与所述多个多边形配对的多个多边形曝光剂量。

    Multiple-grid exposure method
    8.
    发明授权
    Multiple-grid exposure method 有权
    多栅曝光法

    公开(公告)号：US08828632B2

    公开(公告)日：2014-09-09

    申请号：US14017749

    申请日：2013-09-04

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Wen-Chuan Wang ,  Shy-Jay Lin ,  Pei-Yi Liu ,  Jaw-Jung Shin ,  Burn Jeng Lin

    IPC分类号： G03F9/00 ,  G03F7/20

    CPC分类号： G03F7/2022 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/20 ,  G03F7/704 ,  H01J37/3026 ,  H01J37/3174 ,  Y10S430/143

    摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes receiving an integrated circuit (IC) layout design including a target pattern on a grid. The method further includes receiving a multiple-grid structure. The multiple-grid structure includes a number of exposure grid segments offset one from the other by an offset amount in a first direction. The method further includes performing a multiple-grid exposure to expose the target pattern on a substrate and thereby form a circuit feature pattern on the substrate. Performing the multiple-grid exposure includes scanning the substrate with the multiple-grid structure in a second direction such that a sub-pixel shift of the exposed target pattern occurs in the first direction, and using a delta time (Δt) such that a sub-pixel shift of the exposed target pattern occurs in the second direction.

    摘要翻译： 公开了一种制造半导体器件的方法。 一种示例性方法包括接收包括网格上的目标图案的集成电路（IC）布局设计。 该方法还包括接收多网格结构。 多栅格结构包括多个曝光网格段，其在第一方向上彼此偏移一个偏移量。 该方法还包括执行多栅格曝光以将衬底上的目标图案曝光，从而在衬底上形成电路特征图案。 执行多栅格曝光包括在第二方向上以多栅格结构扫描衬底，使得暴露的目标图案的子像素偏移在第一方向上发生，并且使用增量时间（＆Dgr; t）使得 在第二方向上发生曝光的目标图案的子像素偏移。