Invention Grant
- Patent Title: pBIST engine with reduced SRAM testing bus width
- Patent Title (中): 具有减少SRAM测试总线宽度的pBIST引擎
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Application No.: US13709247Application Date: 2012-12-10
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Publication No.: US08977915B2Publication Date: 2015-03-10
- Inventor: Raguram Damodaran , Naveen Bhoria , Aman Kokrady
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; Frederick J. Telecky, Jr.
- Main IPC: G11C29/22
- IPC: G11C29/22 ; G11C29/16 ; G11C29/54 ; G11C11/41 ; G11C29/04
Abstract:
A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.
Public/Granted literature
- US20140164856A1 pBIST ENGINE WITH REDUCED SRAM TESTING BUS WIDTH Public/Granted day:2014-06-12
Information query
