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    System and method for providing adjustable read margins in a semiconductor memory
    2.
    发明授权
    System and method for providing adjustable read margins in a semiconductor memory 有权
    用于在半导体存储器中提供可调读取余量的系统和方法

    公开(公告)号：US07458005B1

    公开(公告)日：2008-11-25

    申请号：US11524691

    申请日：2006-09-21

    申请人： Alex Shubat

    发明人： Alex Shubat

    IPC分类号： G11C29/22 ,  G11C29/40

    CPC分类号： G11C29/026 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004

    摘要： A system and method for effectuating a self-timed clock (STC) loop for memory access operations. In one embodiment, the method includes configuring a particular access margin value setting based on configuration data of at least one memory instance of a memory device; and applying the particular access margin value setting to a reference cell assembly associated with the at least one memory instance for facilitating generation of a self-timed clock signal that is optimized for the at least one memory instance.

    摘要翻译： 用于实现用于存储器访问操作的自定时钟（STC）循环的系统和方法。 在一个实施例中，该方法包括基于存储器件的至少一个存储器实例的配置数据来配置特定访问边缘值设置; 以及将所述特定访问边缘值设置应用于与所述至少一个存储器实例相关联的参考单元组件，以便于为所述至少一个存储器实例优化的自定时钟信号的产生。

    Frequency independent scan chain
    3.
    发明授权
    Frequency independent scan chain 失效
    频率独立扫描链

    公开(公告)号：US5701335A

    公开(公告)日：1997-12-23

    申请号：US658911

    申请日：1996-05-31

    申请人： Alexander J. Neudeck

    发明人： Alexander J. Neudeck

    IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C19/00 ,  G11C29/22

    CPC分类号： G11C19/00 ,  G01R31/318552

    摘要： A shift register is clocked by propagating two clock networks in opposite directions: one from input towards the output, the other from the output towards the input. The parasitic delays at the end of these networks are picked to be approximately equal. An extra latch is added to the shift register where the two clock networks meet to prevent a race condition. Both clock networks consist of non-overlapping clocks. Non-overlapping clock generator circuits are used to restore the non-overlap of the clocks when parasitic effects start to cause clock overlap as the clocks are propagated over long distances. An extra latch in the shift register at the non-overlapping clock generators prevents the delay of the non-overlapping clock generator from causing a race condition.

    摘要翻译： 移位寄存器通过以相反方向传播两个时钟网络来计时：一个从输入到输出，另一个从输出到输入。 这些网络末端的寄生延迟被大致相等。 一个额外的锁存器被添加到两个时钟网络相交的移位寄存器，以防止竞争条件。 两个时钟网络由非重叠时钟组成。 不重叠的时钟发生器电路用于恢复时钟的非重叠，当寄生效应开始引起时钟重叠，因为时钟在长距离上传播。 在非重叠时钟发生器处的移位寄存器中的额外锁存器防止不重叠的时钟发生器的延迟引起竞争条件。

    Recirculating loop memory array fault locator
    4.
    发明授权
    Recirculating loop memory array fault locator 失效
    循环回路存储器阵列故障定位器

    公开(公告)号：US4313199A

    公开(公告)日：1982-01-26

    申请号：US163374

    申请日：1980-06-26

    申请人： Frederick J. Aichelmann, Jr. ,  Bruce E. Bachman

    发明人： Frederick J. Aichelmann, Jr. ,  Bruce E. Bachman

    IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/22 ,  G11C29/56 ,  G06F11/16

    CPC分类号： G11C29/003

    摘要： Apparatus is disclosed for quickly testing memory arrays of multiple recirculating loop memory elements and for locating faulty elements, if any, within designated subdivisions of said array. All loops are loaded with identical test bits. The loaded data is verified and faulty elements, if any, are located by means of a plurality of comparison AND gates. Each gate is connected to the output of a respective subdivision of the array elements and produces a first output signal when all such outputs are identical (on a serial bit-by-bit basis) and produces a second output signal when all said outputs are not identical. The output signals from the respective comparison AND gates are sensed in serial succession to locate the array subdivision containing any faulty elements.

    摘要翻译： 公开了用于快速测试多个循环回路存储器元件的存储器阵列并且用于定位在所述阵列的指定子部分内的有缺陷的元件（如果有的话）的装置。 所有环路都装有相同的测试位。 验证加载的数据，并通过多个比较AND门来定位故障元件（如果有的话）。 每个门连接到阵列元件的相应细分的输出，并且当所有这样的输出相同时（在逐个串行的比特上）产生第一输出信号，并且当所有所述输出不是时，产生第二输出信号 相同。 来自各个比较AND门的输出信号被连续地感测以定位包含任何有缺陷的元件的阵列细分。

    Memory system having memory ranks and related tuning method
    5.
    发明授权
    Memory system having memory ranks and related tuning method 有权
    内存系统具有内存等级和相关的调优方法

    公开(公告)号：US09047929B2

    公开(公告)日：2015-06-02

    申请号：US13967506

    申请日：2013-08-15

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Eunsung Seo ,  Chul-Sung Park ,  Chi-Sung Oh

    IPC分类号： G11C29/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02

    CPC分类号： G11C11/4076 ,  G11C7/10 ,  G11C11/4093 ,  G11C17/16 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/22

    摘要： A memory device comprises at least two memory ranks sharing input/output lines, at least one mode register configured to store bits used to tune delays of data signals of the at least two ranks output through the input/output lines, a controller configured to determine tuning parameters for the data signals based on the stored bits in the at least one mode register, the tuning parameters comprising at least the delays of the data signals, and at least one nonvolatile memory disposed in at least one of the at least two memory ranks and configured to store the tuning parameters.

    摘要翻译： 存储器装置包括共享输入/输出线的至少两个存储器等级，至少一个模式寄存器，被配置为存储用于调整通过输入/输出线输出的至少两个等级的数据信号延迟的位;控制器，被配置为确定 基于所述至少一个模式寄存器中存储的比特来调整所述数据信号的参数，所述调整参数至少包括所述数据信号的延迟，以及至少一个非易失性存储器，其被布置在所述至少两个存储器排中的至少一个中 并且被配置为存储调谐参数。

    pBIST engine with reduced SRAM testing bus width
    6.
    发明授权
    pBIST engine with reduced SRAM testing bus width 有权
    具有减少SRAM测试总线宽度的pBIST引擎

    公开(公告)号：US08977915B2

    公开(公告)日：2015-03-10

    申请号：US13709247

    申请日：2012-12-10

    申请人： Texas Instruments Incorporated

    发明人： Raguram Damodaran ,  Naveen Bhoria ,  Aman Kokrady

    IPC分类号： G11C29/22 ,  G11C29/16 ,  G11C29/54 ,  G11C11/41 ,  G11C29/04

    CPC分类号： G11C29/16 ,  G11C11/41 ,  G11C2029/0401

    摘要： A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. Test data comparison is performed in a distributed data logging architecture to minimize the number of interconnections between the distributed data loggers and the pBIST.

    摘要翻译： 用于测试嵌入式存储器的可编程内置自测（pBIST）系统，其中被测存储器被并入未与pBIST模块集成的多个子芯片中。 在分布式数据记录架构中执行测试数据比较，以最小化分布式数据记录器和pBIST之间的互连数量。

    Method and apparatus for testing counter and serial access memory
    7.
    发明授权
    Method and apparatus for testing counter and serial access memory 失效
    用于测试计数器和串行存取存储器的方法和装置

    公开(公告)号：US5930186A

    公开(公告)日：1999-07-27

    申请号：US959443

    申请日：1997-10-28

    申请人： Itsuro Iwakiri

    发明人： Itsuro Iwakiri

    IPC分类号： G01R31/28 ,  G01R31/00 ,  G01R31/3185 ,  G06F11/00 ,  G11C29/00 ,  G11C29/02 ,  G11C29/22 ,  H03K21/40 ,  G11C7/00

    CPC分类号： G11C29/02 ,  G01R31/318527 ,  G11C29/003 ,  G06F2201/88

    摘要： In a method for testing a counter, the counter is first set at a predetermined initial value. Then, the counter is incremented in response to the clocks. The number of the clocks is counted until a carry is outputted from the counter to provide an actual counted value. The actual counted value is compared to a reference value, which is calculated in advance. And then, the counter is decided whether to be operating normally or not on the basis of the result of the comparison.

    摘要翻译： 在用于测试计数器的方法中，首先将计数器设置为预定的初始值。 然后，计数器响应于时钟递增。 计数时钟数，直到从计数器输出进位以提供实际计数值。 将实际计数值与预先计算的参考值进行比较。 然后，根据比较结果，确定计数器是否正常运行。

    CHIP DETECTION METHOD AND DEVICE
    9.
    发明申请
    CHIP DETECTION METHOD AND DEVICE 有权

    公开(公告)号：US20220310186A1

    公开(公告)日：2022-09-29

    申请号：US17454620

    申请日：2021-11-11

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Jianbo ZHOU

    IPC分类号： G11C29/22 ,  G11C17/16 ,  G01R31/317

    摘要： A chip detection method includes: providing a chip to be tested, the chip having multiple one-time programmable memories (OTPMs); transmitting a test signal to the chip to maintain the OTPMs in the chip in a latched state; and detecting whether the chip emits a low-light signal, and if yes, determining that an OTPM is leaky. The chip detection method and device can detect an OTPM that is burnt through by mistake, and can also detect an OTPM that has slight leakage, thereby preventing a defective product with a potential burn-through risk from entering a subsequent production process.