Invention Grant
- Patent Title: Method of fabricating semiconductor multi-chip stack packages
- Patent Title (中): 制造半导体多芯片堆叠封装的方法
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Application No.: US14088576Application Date: 2013-11-25
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Publication No.: US08980689B2Publication Date: 2015-03-17
- Inventor: Byoung-Soo Kwak , Cha-Jea Jo , Tae-Je Cho , Sang-Uk Han
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR10-2013-0028026 20130315
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48 ; H01L21/50 ; H01L25/00

Abstract:
Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.
Public/Granted literature
- US20140273350A1 METHOD OF FABRICATING SEMICONDUCTOR MULTI-CHIP STACK PACKAGES Public/Granted day:2014-09-18
Information query
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