公开(公告)号：US10535534B2

公开(公告)日：2020-01-14

申请号：US15586716

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US09376541B2

公开(公告)日：2016-06-28

申请号：US14288997

申请日：2014-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-byoung Kang ,  Kyung-wook Paik ,  Tae-Je Cho ,  Young-kun Jee ,  Sun-kyoung Seo ,  Yong-won Choi ,  Ji-won Shin

IPC: H01L23/29 ,  C08K3/08 ,  H01L25/065 ,  H01L23/00

CPC classification number: C08K3/08 ,  C08K2003/0893 ,  C08K2201/011 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2929 ,  H01L2224/29318 ,  H01L2224/32505 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/8211

Abstract: A non-conductive material layer, selected from a non-conductive film and a non-conductive polymer paste, and containing a dispersion of zinc (Zn) particles is disclosed, together with semiconductor packages including the non-conductive material layer. The non-conductive material layer contains zinc (Zn) particles having an average particle diameter of about 1 nm to about 200 nm in a non-conductive polymer base material of a film type, and a semiconductor package includes the non-conductive film. By using the non-conductive film and/or the non-conductive paste containing the zinc dispersion, e a semiconductor package having excellent electric connection properties and high reliability may be manufactured through simple processes at low manufacturing costs.

Abstract translation: 公开了一种选自非导电膜和非导电聚合物浆料并含有锌（Zn）颗粒的分散体的非导电材料层以及包括非导电材料层的半导体封装。 非导电材料层在薄膜型非导电性聚合物基材中含有平均粒径为约1nm〜约200nm的锌（Zn）颗粒，半导体封装包括非导电膜。 通过使用含有锌分散体的非导电性膜和/或非导电性糊剂，可以以低制造成本通过简单的工艺制造具有优异的电连接性能和高可靠性的半导体封装。

公开(公告)号：US09343361B2

公开(公告)日：2016-05-17

申请号：US14072777

申请日：2013-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC: H01L21/76 ,  H01L21/326 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

公开(公告)号：US09171825B2

公开(公告)日：2015-10-27

申请号：US14488707

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Sick Park ,  In-Young Lee ,  Byoung-Soo Kwak ,  Min-Soo Kim ,  Sang-Wook Park ,  Tae-Je Cho

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip.

Abstract translation: 一种半导体器件及其制造方法包括提供具有第一连接端子的第一半导体芯片，提供第二半导体芯片，该第二半导体芯片包括彼此相对的顶表面和底表面，并且具有第二连接端子和形成的膜型第一底部填充材料 在其底面上，通过使用第一连接端子将第一半导体芯片接合到安装基板，通过使用第一底部填充材料接合第一半导体芯片和第二半导体芯片，以及形成填充第二底部填充材料之间的空间的第二底部填充材料 安装基板和第一半导体芯片，并且覆盖第一半导体芯片的侧表面和第二半导体芯片的至少一部分侧表面。

公开(公告)号：US20130267057A1

公开(公告)日：2013-10-10

申请号：US13909160

申请日：2013-06-04

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC: H01L31/18

CPC classification number: H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘合图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。

公开(公告)号：US09666551B1

公开(公告)日：2017-05-30

申请号：US15236814

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Seung-kwan Ryu ,  Cha-jea Jo ,  Tae-Je Cho

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L24/14 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

公开(公告)号：US09618716B2

公开(公告)日：2017-04-11

申请号：US14988739

申请日：2016-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Cheon Park ,  Cha-Jea Jo ,  Tae-Je Cho

IPC: G02B6/43 ,  G02B6/44 ,  G02B6/122 ,  G02B6/42

CPC classification number: G02B6/43 ,  G02B6/1226 ,  G02B6/428 ,  G02B6/4283 ,  G02B6/4295 ,  G02B6/4416 ,  Y02E10/52

Abstract: A photonic integrated circuit is provided. The photonic integrated circuit includes a substrate having a through hole interconnecting a first surface and a second surface; a transmission wire passing through the through hole and including an optical transmission structure and an electrical transmission structure; and an optical-to-electrical converter connected to the optical transmission structure of the transmission wire on the first surface.

公开(公告)号：US20150102485A1

公开(公告)日：2015-04-16

申请号：US14288997

申请日：2014-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-byoung Kang ,  Kyung-wook Paik ,  Tae-Je Cho ,  Young-kun Jee ,  Sun-kyoung Seo ,  Yong-won Choi ,  Ji-won Shin

IPC: H01L23/29 ,  H01L23/538 ,  C08K3/08 ,  H01L23/50

CPC classification number: C08K3/08 ,  C08K2003/0893 ,  C08K2201/011 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2929 ,  H01L2224/29318 ,  H01L2224/32505 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/8211

Abstract: A non-conductive material layer, selected from a non-conductive film and a non-conductive polymer paste, and containing a dispersion of zinc (Zn) particles is disclosed, together with semiconductor packages including the non-conductive material layer. The non-conductive material layer contains zinc (Zn) particles having an average particle diameter of about 1 nm to about 200 nm in a non-conductive polymer base material of a film type, and a semiconductor package includes the non-conductive film. By using the non-conductive film and/or the non-conductive paste containing the zinc dispersion, e a semiconductor package having excellent electric connection properties and high reliability may be manufactured through simple processes at low manufacturing costs.

Abstract translation: 公开了一种选自非导电膜和非导电聚合物浆料并含有锌（Zn）颗粒的分散体的非导电材料层以及包括非导电材料层的半导体封装。 非导电材料层在薄膜型非导电性聚合物基材中含有平均粒径为约1nm〜约200nm的锌（Zn）颗粒，半导体封装包括非导电膜。 通过使用含有锌分散体的非导电性膜和/或非导电性糊剂，可以以低制造成本通过简单的工艺制造具有优异的电连接性能和高可靠性的半导体封装。

公开(公告)号：US08852988B2

公开(公告)日：2014-10-07

申请号：US13909160

申请日：2013-06-04

Applicant: Samsung Electronics Co., Ltd

Inventor： Hyung-Sun Jang ,  Woon-Seong Kwon ,  Tae-Je Cho ,  Un-Byoung Kang ,  Jung-Hwan Kim

IPC: H01L31/18 ,  H01L27/146

CPC classification number: H01L31/18 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14687 ,  H01L2224/13

Abstract: A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括具有第一表面，第二表面和像素区域的半导体芯片，设置在第一表面上的第一粘附图案，设置在第一粘附图案和像素区域之间并设置在第一表面上的第二粘合图案，以及 设置在第二表面上的外部连接端子，其中第二粘合图案和外部连接端子彼此重叠设置。

公开(公告)号：US09905538B2

公开(公告)日：2018-02-27

申请号：US15402521

申请日：2017-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Byung-Hyug Roh

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1413 ,  H01L2224/14181 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1713 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.