公开(公告)号：US20170330767A1

公开(公告)日：2017-11-16

申请号：US15586716

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je CHO ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H01L21/48 ,  C23C14/58 ,  C23C14/34 ,  C23C14/20 ,  C23C14/06 ,  C23C14/04 ,  C23C14/02 ,  B05D7/00 ,  B05D3/02 ,  B05D1/38 ,  B05D1/32 ,  B05D1/00

CPC classification number: H01L21/4857 ,  B05D1/005 ,  B05D1/32 ,  B05D1/38 ,  B05D3/0209 ,  B05D7/546 ,  C23C14/024 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/205 ,  C23C14/34 ,  C23C14/588 ,  C23C18/00 ,  C23C18/38 ,  H01L21/486 ,  H01L23/4334 ,  H01L23/473 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/0588 ,  H01L2924/01047 ,  H01L2224/81

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US09618716B2

公开(公告)日：2017-04-11

申请号：US14988739

申请日：2016-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Cheon Park ,  Cha-Jea Jo ,  Tae-Je Cho

IPC: G02B6/43 ,  G02B6/44 ,  G02B6/122 ,  G02B6/42

CPC classification number: G02B6/43 ,  G02B6/1226 ,  G02B6/428 ,  G02B6/4283 ,  G02B6/4295 ,  G02B6/4416 ,  Y02E10/52

Abstract: A photonic integrated circuit is provided. The photonic integrated circuit includes a substrate having a through hole interconnecting a first surface and a second surface; a transmission wire passing through the through hole and including an optical transmission structure and an electrical transmission structure; and an optical-to-electrical converter connected to the optical transmission structure of the transmission wire on the first surface.

公开(公告)号：US10750112B2

公开(公告)日：2020-08-18

申请号：US16129010

申请日：2018-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hwang Kim ,  Hyo-Eun Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Sang-Uk Han

IPC: H04N5/369 ,  H04N5/225 ,  G02B5/20 ,  H01L27/146

Abstract: A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.

公开(公告)号：US08980689B2

公开(公告)日：2015-03-17

申请号：US14088576

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Soo Kwak ,  Cha-Jea Jo ,  Tae-Je Cho ,  Sang-Uk Han

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

Abstract translation: 提供一种制造多芯片堆叠封装的方法。 该方法包括制备具有单体下部芯片衬底的单体下部芯片，其具有第一表面和与第一表面相对设置的第二表面，将单元封装衬底粘合到单体下部芯片衬底的第一表面上以形成 单体衬底芯片接合结构，将单体衬底 - 芯片接合结构分离成多个单元衬底 - 芯片接合结构，制备具有单体上片状衬底的单体上片，将多个单元 衬底 - 芯片接合结构到单体上芯片衬底的第一表面上以形成单体半导体芯片堆叠结构，并将单体半导体芯片堆叠结构分离成多个单元半导体芯片堆栈结构。

公开(公告)号：US08912048B2

公开(公告)日：2014-12-16

申请号：US13803662

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Youn Kim ,  Ji-Hwang Kim ,  Hae-Jung Yu ,  Cha-Jea Jo

IPC: H01L21/00 ,  H01L21/82

CPC classification number: H01L21/82 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10332 ,  H01L2924/10333 ,  H01L2924/10335 ,  H01L2924/10523 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/32225 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.

Abstract translation: 制造半导体器件的方法包括：使用载体固定层将半导体衬底附着到载体上，其中半导体衬底包括多个半导体芯片。 该方法还包括在相邻芯片之间形成间隙。 可以使用一种或多种化学品或光来形成间隙，所述化学物质或光用于去除半导体衬底的部分以暴露载体固定层。 然后移除载体固定层的附加部分以允许将芯片从载体上移除。

公开(公告)号：US10535534B2

公开(公告)日：2020-01-14

申请号：US15586716

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US09159659B2

公开(公告)日：2015-10-13

申请号：US13835969

申请日：2013-03-15

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Sang-Won Kim ,  Kwang-Chul Choi ,  Hyun-Jung Song ,  Cha-Jea Jo ,  Eun-Kyoung Choi ,  Ji-Seok Hong

IPC: H01L23/49 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.

Abstract translation: 半导体封装包括第一半导体芯片，第二半导体芯片和密封构件。 第一半导体芯片包括具有与第一表面相对的第一表面和第二表面的基板，并且具有从第二表面以预定深度延伸的开口，以及从厚度方向从第一表面延伸的多个贯穿电极 通孔的端部通过开口的底表面露出。 第二半导体芯片被容纳在开口中并安装在开口的底表面上。 密封构件覆盖开口中的第二半导体芯片。

公开(公告)号：US11018026B2

公开(公告)日：2021-05-25

申请号：US16699283

申请日：2019-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je Cho ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H05K1/11 ,  H05K1/18 ,  H01L21/48 ,  H05K3/46 ,  C23C18/00 ,  H01L23/433 ,  H01L23/498 ,  B05D1/00 ,  B05D1/32 ,  B05D1/38 ,  B05D3/02 ,  B05D7/00 ,  C23C14/02 ,  C23C14/04 ,  C23C14/06 ,  C23C14/20 ,  C23C14/34 ,  C23C14/58 ,  C23C18/38 ,  H01L23/00 ,  H01L25/03 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H05K1/14

Abstract: A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.

公开(公告)号：US10483150B2

公开(公告)日：2019-11-19

申请号：US15349327

申请日：2016-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun-Ah Lee ,  Ji-Hwan Hwang ,  Cha-Jea Jo ,  Dong-Han Kim ,  Seung-Kon Mok

IPC: H01L21/683 ,  H01L21/67 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An apparatus for stacking semiconductor chips includes a push member configured to apply pressure to a semiconductor chip disposed on a substrate. The push member includes a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate. The push plate includes a central portion having an area smaller than an area of an upper side of the semiconductor chip, and a plurality of protrusions disposed at respective ends of the central portion.

公开(公告)号：US10224272B2

公开(公告)日：2019-03-05

申请号：US16004539

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hwang Kim ,  Jong-Bo Shim ,  Cha-Jea Jo ,  Won-Il Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.