An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.