公开(公告)号：US20140368667A1

公开(公告)日：2014-12-18

申请号：US14142848

申请日：2013-12-29

Applicant: Intel Corporation

Inventor： Steven A. Peterson ,  Haran Thanigasalam ,  Sriram Balasubrahmanyam

IPC: H04N17/00

CPC classification number: H04N17/002 ,  G06F13/4278 ,  H04L7/0066 ,  H04L7/10 ,  H04N5/23203

Abstract: Apparatus, methods, and systems are herein described for providing a method for calibrating a channel by employing a training sequence during at least one blanking interval. In one embodiment, an apparatus includes a first control logic to send a command to generate a predetermined data pattern during at least one blanking interval. In addition, the apparatus includes a second control logic to determine whether a received data pattern matches the predetermined data pattern.

Abstract translation: 本文描述的装置，方法和系统用于提供一种通过在至少一个消隐间隔期间采用训练序列校准信道的方法。 在一个实施例中，一种装置包括第一控制逻辑，用于在至少一个消隐间隔期间发送命令以产生预定的数据模式。 另外，该装置包括用于确定接收到的数据模式是否与预定数据模式匹配的第二控制逻辑。

公开(公告)号：US08982999B2

公开(公告)日：2015-03-17

申请号：US13632082

申请日：2012-09-30

Applicant: Intel Corporation

Inventor： Kiriti Bhagavathula ,  Chunyu Zhang ,  Steven A. Peterson

IPC: H03K9/00 ,  H04L7/00 ,  H04L25/02 ,  H04L25/49 ,  H04L25/03

CPC classification number: H04L7/0066 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03878 ,  H04L25/4908

Abstract: An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.

Abstract translation: 本发明的实施例包括具有减少的误差项和进入抖动跟踪的接收机，其提高了抖动容限。 实施例提供了基于电压积分器的这些益处，该电压积分器在不使用PLL，PI，CDR等的情况下从输入信号中恢复数据和时钟信息。 实施例基于时间积分器提供这些益处，该时间积分器使用数字逻辑，来自输入信号的数据和时钟信息，而不使用PLL，PI，CDR等。 本文描述了其它实施例。