Invention Grant
- Patent Title: Method for on-wafer high voltage testing of semiconductor devices
- Patent Title (中): 半导体器件的片上高压测试方法
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Application No.: US13914060Application Date: 2013-06-10
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Publication No.: US08988097B2Publication Date: 2015-03-24
- Inventor: Andrew P. Ritenour
- Applicant: RF Micro Devices, Inc.
- Applicant Address: US NC Greensboro
- Assignee: RF Micro Devices, Inc.
- Current Assignee: RF Micro Devices, Inc.
- Current Assignee Address: US NC Greensboro
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01L21/66

Abstract:
A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices.
Public/Granted literature
- US20140057372A1 METHOD FOR ON-WAFER HIGH VOLTAGE TESTING OF SEMICONDUCTOR DEVICES Public/Granted day:2014-02-27
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