发明授权
- 专利标题： Test structure and method of testing electrical characteristics of through vias
- 专利标题（中）： 通孔测试电气特性的测试结构和方法
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申请号： US13297779申请日： 2011-11-16
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公开(公告)号： US08993432B2公开(公告)日： 2015-03-31
- 发明人: Shang-Yun Hou , Wei-Cheng Wu , Hsien-Pin Hu , Jung Cheng Ko , Shin-Puu Jeng , Chen-Hua Yu , Kim Hong Chen
- 申请人： Shang-Yun Hou , Wei-Cheng Wu , Hsien-Pin Hu , Jung Cheng Ko , Shin-Puu Jeng , Chen-Hua Yu , Kim Hong Chen
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Slater & Matsil, L.L.P.
- 主分类号： H01L21/44
- IPC分类号： H01L21/44 ; H01L21/66 ; H01L21/768 ; H01L23/00
摘要：
A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.
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