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公开(公告)号:US08896089B2
公开(公告)日:2014-11-25
申请号:US13292792
申请日:2011-11-09
申请人: Tzu-Wei Chiu , Tzu-Yu Wang , Wei-Cheng Wu , Chun-Yi Liu , Hsien-Pin Hu , Shang-Yun Hou
发明人: Tzu-Wei Chiu , Tzu-Yu Wang , Wei-Cheng Wu , Chun-Yi Liu , Hsien-Pin Hu , Shang-Yun Hou
IPC分类号: H01L23/52 , H01L21/82 , H01L23/498 , H01L23/538 , H01L23/00 , H01L23/525 , H01L23/48 , H01L23/31
CPC分类号: H01L23/49827 , H01L23/3128 , H01L23/481 , H01L23/525 , H01L23/5256 , H01L23/5382 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/13184 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81192 , H01L2924/00011 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/157 , H01L2924/00 , H01L2224/81805
摘要: Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.
摘要翻译: 公开了半导体器件用插入件及其制造方法。 在一个实施例中,插入器包括衬底,设置在衬底上的接触焊盘以及耦合到接触焊盘的衬底中的第一通孔。 第一保险丝耦合到第一通孔。 衬底中的第二通孔耦合到接触焊盘,并且第二保险丝耦合到第二通孔。
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公开(公告)号:US08797057B2
公开(公告)日:2014-08-05
申请号:US13025931
申请日:2011-02-11
申请人: Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
发明人: Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
IPC分类号: G01R31/00
CPC分类号: G01R31/2896 , G01R1/0416 , G01R31/2601 , G01R31/2884 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02377 , H01L2224/0392 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05552 , H01L2224/05568 , H01L2224/05655 , H01L2224/0614 , H01L2224/0616 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13083 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16238 , H01L2924/20752 , H01L2924/00012 , H01L2924/00014 , H01L2924/01047 , H01L2924/014
摘要: Test structures for performing electrical tests of devices under one or more microbumps are provided. Each test structure includes at least one microbump pad and a test pad. The microbump pad is a part of a metal pad connected to an interconnect for a device. A width of the microbump pad is equal to or less than about 50 μm. The test pad is connected to the at least one microbump pad. The test pad has a size large enough to allow circuit probing of the device. The test pad is another part of the metal pad. A width of the test pad is greater than the at least one microbump pad.
摘要翻译: 提供用于对一个或多个微丸下的装置进行电测试的测试结构。 每个测试结构包括至少一个微型块和测试垫。 微型焊盘是与设备的互连件连接的金属焊盘的一部分。 微型焊盘的宽度等于或小于约50μm。 测试垫连接到至少一个微型块。 测试垫的尺寸足够大以允许设备的电路探测。 测试垫是金属垫的另一部分。 测试垫的宽度大于至少一个微小块垫。
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公开(公告)号:US20120104578A1
公开(公告)日:2012-05-03
申请号:US13342583
申请日:2012-01-03
申请人: Hsien-Pin Hu , Chen-Hu Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
发明人: Hsien-Pin Hu , Chen-Hu Yu , Shin-Puu Jeng , Shang-Yun Hou , Jing-Cheng Lin , Wen-Chih Chiou , Hung-Jung Tu
IPC分类号: H01L23/495
CPC分类号: H01L21/561 , H01L21/486 , H01L23/147 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/97 , H01L25/0655 , H01L2224/05001 , H01L2224/05027 , H01L2224/05571 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/05541 , H01L2224/05005 , H01L2224/05599 , H01L2224/05099
摘要: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.
摘要翻译: 一种方法包括提供包括衬底的中介层晶片,以及从衬底的前表面延伸到衬底中的多个贯通衬底通孔(TSV)。 多个管芯结合到插入件晶片的前表面上。 在结合多个模具的步骤之后,在基板的背面进行研磨以暴露多个TSV。 多个金属凸块形成在插入器晶片的背面并电耦合到多个TSV。
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公开(公告)号:US20110298551A1
公开(公告)日:2011-12-08
申请号:US12795734
申请日:2010-06-08
申请人: Hsiao-Tsung YEN , Hsien-Pin HU , Jhe-Ching LU , Chin-Wei KUO , Ming-Fa CHEN , Sally LIU
发明人: Hsiao-Tsung YEN , Hsien-Pin HU , Jhe-Ching LU , Chin-Wei KUO , Ming-Fa CHEN , Sally LIU
IPC分类号: H03B5/12 , H01L21/329 , H01L29/93
CPC分类号: H01L27/016 , H01L29/93
摘要: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
摘要翻译: 三维集成电路包括半导体衬底,其中衬底具有延伸穿过衬底的第一表面和第二表面的开口,并且第一表面和第二表面与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔(TSV)。 有源电路设置在衬底的第一表面上,电感器设置在衬底的第二表面上,并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管,使得导电材料邻近介电层设置,以及设置在TSV周围的杂质注入区域,使得介电层形成在 杂质注入区和TSV。
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公开(公告)号:US10297550B2
公开(公告)日:2019-05-21
申请号:US12774558
申请日:2010-05-05
申请人: Hsien-Pin Hu , Chen-Hua Yu , Ming-Fa Chen , Jing-Cheng Lin , Jiun Ren Lai , Yung-Chi Lin
发明人: Hsien-Pin Hu , Chen-Hua Yu , Ming-Fa Chen , Jing-Cheng Lin , Jiun Ren Lai , Yung-Chi Lin
IPC分类号: H01L23/538 , H01L23/488 , H01L21/56 , H01L21/683 , H01L23/14 , H01L23/31 , H01L23/498 , H01L23/00 , H01L25/065
摘要: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.
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公开(公告)号:US09128123B2
公开(公告)日:2015-09-08
申请号:US13198223
申请日:2011-08-04
申请人: Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng
发明人: Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号: H01L23/528 , G01R1/073 , H01L21/66 , H01L21/56 , H01L21/683 , H01L23/498
CPC分类号: H01L22/32 , G01R1/07378 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/6835 , H01L22/30 , H01L22/34 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/585 , H01L2221/68331 , H01L2224/05001 , H01L2224/05026 , H01L2224/05572 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00 , H01L2224/05124 , H01L2224/05147
摘要: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
摘要翻译: 本公开的实施例是包括插入器的结构。 插入器具有沿着插入件的周边延伸的测试结构,并且测试结构的至少一部分处于第一再分配元件中。 第一再分配元件位于中介层的衬底的第一表面上。 测试结构是中间的并且电耦合到至少两个探针焊盘。
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公开(公告)号:US08878182B2
公开(公告)日:2014-11-04
申请号:US13272004
申请日:2011-10-12
申请人: Tzu-Yu Wang , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Hsien-Pin Hu , Wei-Cheng Wu , Li-Han Hsu , Meng-Han Lee
发明人: Tzu-Yu Wang , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Hsien-Pin Hu , Wei-Cheng Wu , Li-Han Hsu , Meng-Han Lee
IPC分类号: H01L23/58 , H01L21/66 , H01L23/498 , H01L23/538 , H01L23/00 , H01L25/065 , H01L23/31
CPC分类号: H01L22/32 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/5384 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0655 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01L2924/014 , H01L2924/00012 , H01L2924/00
摘要: An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad.
摘要翻译: 插入器包括在插入件的第一侧上的第一表面和在插入件的第二侧上的第二表面,其中第一和第二侧是相对的两侧。 第一探针垫设置在第一表面。 电连接器设置在第一表面处,其中电连接器被配置为用于接合。 通孔设置在插入器中。 前侧连接设置在插入件的第一侧上,其中前侧连接将通孔电连接到探针垫。
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公开(公告)号:US20130120018A1
公开(公告)日:2013-05-16
申请号:US13297779
申请日:2011-11-16
申请人: Shang-Yun Hou , Wei-Cheng Wu , Hsien-Pin Hu , Jung Cheng Ko , Shin-Puu Jeng , Chen-Hua Yu , Kim Hong Chen
发明人: Shang-Yun Hou , Wei-Cheng Wu , Hsien-Pin Hu , Jung Cheng Ko , Shin-Puu Jeng , Chen-Hua Yu , Kim Hong Chen
CPC分类号: H05K1/115 , H01L21/76898 , H01L22/14 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/0557 , H01L2224/1147 , H01L2224/13025 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2924/00014 , H01L2924/01322 , H01L2924/12042 , H05K1/0298 , H05K2201/2081 , H01L2924/01082 , H01L2224/05552 , H01L2924/00
摘要: A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.
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公开(公告)号:US08362591B2
公开(公告)日:2013-01-29
申请号:US12795734
申请日:2010-06-08
申请人: Hsiao-Tsung Yen , Hsien-Pin Hu , Jhe-Ching Lu , Chin-Wei Kuo , Ming-Fa Chen , Sally Liu
发明人: Hsiao-Tsung Yen , Hsien-Pin Hu , Jhe-Ching Lu , Chin-Wei Kuo , Ming-Fa Chen , Sally Liu
IPC分类号: H01L29/93
CPC分类号: H01L27/016 , H01L29/93
摘要: A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.
摘要翻译: 三维集成电路包括半导体衬底,其中衬底具有延伸穿过衬底的第一表面和第二表面的开口,并且其中第一表面和第二表面是与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔(TSV)。 有源电路设置在衬底的第一表面上,电感器设置在衬底的第二表面上,并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管,使得导电材料邻近介电层设置,以及设置在TSV周围的杂质注入区域,使得介电层形成在 杂质注入区和TSV。
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公开(公告)号:US20120305916A1
公开(公告)日:2012-12-06
申请号:US13198223
申请日:2011-08-04
申请人: Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng
发明人: Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号: H01L23/528
CPC分类号: H01L22/32 , G01R1/07378 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/6835 , H01L22/30 , H01L22/34 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/585 , H01L2221/68331 , H01L2224/05001 , H01L2224/05026 , H01L2224/05572 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00 , H01L2224/05124 , H01L2224/05147
摘要: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
摘要翻译: 本公开的实施例是包括插入器的结构。 插入器具有沿着插入件的周边延伸的测试结构,并且测试结构的至少一部分处于第一再分配元件中。 第一再分配元件位于中介层的衬底的第一表面上。 测试结构是中间的并且电耦合到至少两个探针焊盘。
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