Invention Grant
- Patent Title: Semiconductor device packages with solder joint enhancement elements
- Patent Title (中): 具有焊点增强元件的半导体器件封装
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Application No.: US13953328Application Date: 2013-07-29
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Publication No.: US08994156B2Publication Date: 2015-03-31
- Inventor: Po-Shing Chiang , Ping-Cheng Hu , Yu-Fang Tsai
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: Klein, O'Neill & Singh, LLP
- Priority: TW100123897A 20110706
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/00 ; H05K5/02 ; H01L23/488 ; H01L23/00 ; H01L21/48 ; H01L21/56

Abstract:
Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.
Public/Granted literature
- US20130307157A1 SEMICONDUCTOR DEVICE PACKAGES WITH SOLDER JOINT ENHANCEMENT ELEMENT AND RELATED METHODS Public/Granted day:2013-11-21
Information query
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