Invention Grant
US08995166B2 Multi-level memory array having resistive elements for multi-bit data storage
有权
具有用于多位数据存储的电阻元件的多级存储器阵列
- Patent Title: Multi-level memory array having resistive elements for multi-bit data storage
- Patent Title (中): 具有用于多位数据存储的电阻元件的多级存储器阵列
-
Application No.: US13721279Application Date: 2012-12-20
-
Publication No.: US08995166B2Publication Date: 2015-03-31
- Inventor: Dipankar Pramanik , David E Lazovsky , Tim Minvielle , Takeshi Yamaguchi
- Applicant: Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
- Applicant Address: US CA San Jose JP Tokyo US CA Milpitas
- Assignee: Intermolecular, Inc.,Kabushiki Kaisha Toshiba,SanDisk 3D LLC
- Current Assignee: Intermolecular, Inc.,Kabushiki Kaisha Toshiba,SanDisk 3D LLC
- Current Assignee Address: US CA San Jose JP Tokyo US CA Milpitas
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C13/00 ; G11C11/56 ; H01L45/00 ; H01L27/24

Abstract:
A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.
Public/Granted literature
- US20140177315A1 Multi-Level Memory Array Having Resistive Elements For Multi-Bit Data Storage Public/Granted day:2014-06-26
Information query