Invention Grant
- Patent Title: Error correction code rate management for nonvolatile memory
- Patent Title (中): 非易失性存储器的纠错码率管理
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Application No.: US13798696Application Date: 2013-03-13
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Publication No.: US08996961B2Publication Date: 2015-03-31
- Inventor: Zhengang Chen , Jeremy Werner , Earl T. Cohen , Ning Chen , AbdelHakim S. Alhussien , Erich F. Haratsch
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agent Christopher P. Maiorana, PC
- Main IPC: G11C29/10
- IPC: G11C29/10 ; G06F11/10

Abstract:
An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold.
Public/Granted literature
- US20140164880A1 ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY Public/Granted day:2014-06-12
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