Invention Grant
US08996961B2 Error correction code rate management for nonvolatile memory 有权
非易失性存储器的纠错码率管理

Error correction code rate management for nonvolatile memory
Abstract:
An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold.
Public/Granted literature
Information query
Patent Agency Ranking
0/0