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公开(公告)号：US10707900B2
公开(公告)日：2020-07-07
申请号：US16389551
申请日：2019-04-19
摘要： A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
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公开(公告)号：US10410736B2
公开(公告)日：2019-09-10
申请号：US15423692
申请日：2017-02-03
发明人： Zhengang Chen , David Patmore , Yingji Ju , Erich F. Haratsch
IPC分类号： G11C29/42 , G11C29/44 , G11C29/36 , H03M13/11 , H04L1/00 , G06F11/00 , G11C7/10 , G06F3/06 , G11C11/56 , G11C29/52 , G11C16/10 , G11C16/00
摘要： An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
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公开(公告)号：US10396817B2
公开(公告)日：2019-08-27
申请号：US15368973
申请日：2016-12-05
摘要： A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.
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公开(公告)号：US10353622B2
公开(公告)日：2019-07-16
申请号：US15448103
申请日：2017-03-02
摘要： Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.
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公开(公告)号：US10303402B2
公开(公告)日：2019-05-28
申请号：US15226182
申请日：2016-08-02
摘要： A data storage device includes at least one data storage medium and a controller that is operably coupled to the at least one data storage medium. The controller receives the bit stream in a data storage device and performs a first level of compression on the received bit stream to obtain a symbol frame including a plurality of symbols. The controller encodes an initial portion of the plurality of symbols contained in the symbol frame by a fixed encoding scheme. The controller also collects statistics for the initial portion of the symbol frame. The controller then selects at least one data compression algorithm based on the collected statistics. The controller then performs compression encoding on a remaining portion of the symbol frame with the selected at least one data compression algorithm.
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公开(公告)号：US10298263B2
公开(公告)日：2019-05-21
申请号：US14218626
申请日：2014-03-18
摘要： A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
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公开(公告)号：US10276247B2
公开(公告)日：2019-04-30
申请号：US15205654
申请日：2016-07-08
发明人： AbdelHakim S. Alhussien , Sundararajan Sankaranarayanan , Thuy Van Nguyen , Ludovic Danjean , Erich F. Haratsch
摘要： Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.
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公开(公告)号：US10180868B2
公开(公告)日：2019-01-15
申请号：US15639019
申请日：2017-06-30
IPC分类号： G06F11/07 , G11C16/08 , G11C11/56 , G11C16/26 , G06F11/10 , G11C16/28 , G11C29/02 , G11C29/52 , H03M13/11 , H03M13/37 , H03M13/00 , G11C29/04
摘要： Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.
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公开(公告)号：US20180166142A1
公开(公告)日：2018-06-14
申请号：US15889536
申请日：2018-02-06
发明人： Yu Cai , Yunxiang Wu , Erich F. Haratsch
CPC分类号： G11C16/3459 , G06F11/1048 , G11C11/56 , G11C11/5628 , G11C16/10 , G11C16/34 , G11C16/349 , G11C29/44 , G11C29/52 , G11C2029/0411
摘要： An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies. Each memory die may have a size less than a total size of the memory and include a plurality of cells. The memory may perform a program operation to write to and verify one or more of the plurality of cells in response to receiving a program command. The controller may be configured to issue the program command to program the plurality of memory dies and to issue the polling status command after issuing the program command to obtain a number of the cells that failed to be verified during the program operation. In response to the polling status command received from the controller, the memory reports a count of a number of bit-lines not having an inhibited state in the write buffer.
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公开(公告)号：US09785499B2
公开(公告)日：2017-10-10
申请号：US14192110
申请日：2014-02-27
发明人： Yu Cai , Yunxiang Wu , Erich F. Haratsch
CPC分类号： G06F11/1048 , G06F3/0616 , G06F11/1016
摘要： An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory.
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