Invention Grant
US09012956B2 Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe
有权
通道SiGe从PFET源极/漏极区域去除,以改善HKMG技术中的硅化物形成,而无需嵌入式SiGe
- Patent Title: Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe
- Patent Title (中): 通道SiGe从PFET源极/漏极区域去除,以改善HKMG技术中的硅化物形成,而无需嵌入式SiGe
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Application No.: US13783517Application Date: 2013-03-04
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Publication No.: US09012956B2Publication Date: 2015-04-21
- Inventor: Stefan Flachowsky , Ralf Richter , Jan Hoentschel
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Amerson Law Firm, PLLC
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/66 ; H01L29/78 ; H01L21/8238

Abstract:
When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.
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