公开(公告)号：US10056376B2

公开(公告)日：2018-08-21

申请号：US15238023

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.

公开(公告)号：US20180040731A1

公开(公告)日：2018-02-08

申请号：US15231105

申请日：2016-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/786 ,  H01L21/324 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02181 ,  H01L21/02356 ,  H01L21/28291 ,  H01L21/324 ,  H01L21/76251 ,  H01L21/76254 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78654

Abstract: A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.

公开(公告)号：US09583240B2

公开(公告)日：2017-02-28

申请号：US14469012

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01C7/10 ,  H01C1/16 ,  H01C7/02 ,  H01C7/04 ,  H01C7/00 ,  H01C17/075

CPC classification number: H01C1/16 ,  H01C7/008 ,  H01C7/021 ,  H01C7/027 ,  H01C7/041 ,  H01C17/075

Abstract: The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.

Abstract translation: 本公开内容涉及包括正温度系数热敏电阻和负温度系数热敏电阻的半导体结构，该正温度系数热敏电阻和负温度系数热敏电阻通过连接元件彼此并联连接，连接元件被构造成使得由并联连接产生的电阻在预定的 温度范围和相应的制造方法。

公开(公告)号：US09490361B2

公开(公告)日：2016-11-08

申请号：US14192158

申请日：2014-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Thilo Scheiper

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/423 ,  H01L29/45 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/78 ,  H01L29/7848

Abstract: Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle α preferably about ≧90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.

Abstract translation: 通过在延伸到半导体衬底的腔中形成非平面MOSFET，可以避免MOSFETS中栅极和感应沟道长度的光刻限制。 栅极绝缘体和沟道区域靠近具有相对于半导体表面的角度α优选地约≥90度的空腔侧壁。 通道长度取决于空腔的底部深度以及与空腔相邻的源极或漏极区域的表面的深度。 相应的漏极或源极位于腔底。 空腔侧壁在其间延伸。 两个深度都不是光刻依赖的。 可以一贯形成非常短的通道，从而提高性能和制造成品率。 源极，漏极和栅极连接被带到相同的表面，使得可以容易地构造复杂的电路。 源区和漏区优选地外延形成，并且应变诱导材料可用于其中以改善沟道载流子迁移率。

公开(公告)号：US09484407B2

公开(公告)日：2016-11-01

申请号：US14469741

申请日：2014-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tim Baldauf ,  Stefan Flachowsky

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/778

CPC classification number: H01L29/068 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7827 ,  H01L29/785

Abstract: A semiconductor device is provided including a semiconductor substrate and a nanowire formed over the semiconductor substrate and wherein the nanowire includes a first layer exhibiting tensile stress and a second layer exhibiting compressive stress.

Abstract translation: 提供了半导体器件，其包括形成在半导体衬底上的半导体衬底和纳米线，并且其中纳米线包括呈现拉伸应力的第一层和呈现压应力的第二层。

公开(公告)号：US20160268426A1

公开(公告)日：2016-09-15

申请号：US15161399

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Abstract translation: 半导体器件包括多个间隔开的翅片，位于多个间隔开的翅片中的每一个之间的介电材料层，以及位于电介质材料层上方并延伸穿过翅片的公共栅极结构。 连续合并的半导体材料区域位于每个散热片上并且位于电介质材料层上方，与公共栅极结构横向间隔开，在翅片之间延伸并物理接触翅片，具有面向公共栅极结构的第一侧壁表面 并且具有与第一侧壁表面相对并且远离公共栅极结构的第二侧壁表面。 应力诱导材料定位在由至少第一侧壁表面，相邻的一对翅片的相对侧壁表面和介电材料层的上表面限定的空间中。

公开(公告)号：US20160254382A1

公开(公告)日：2016-09-01

申请号：US14633351

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Gerd Zschaetzsch

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括形成堆叠在衬底上的叠层。 堆叠包括硅锗层和硅层，其中硅锗层具有第一锗浓度。 堆叠被冷凝以在锗层中产生第二锗浓度，其中第二锗浓度大于第一锗浓度。 形成包括叠层的翅片，并且形成覆盖在翅片上的浇口。

公开(公告)号：US09431508B2

公开(公告)日：2016-08-30

申请号：US14047517

申请日：2013-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Roman Boschke

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7833

Abstract: When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in formation of a metal silicide layer on the surface of the gate electrode and of the source and drain regions of the transistor. The present disclosure improves the manufacturing flow by skipping the gate cap removal process. Metal silicide is only formed on the source and drain regions. The gate electrode is then contacted by forming an aperture through the gate material, leaving the surface of the gate metal layer exposed.

Abstract translation: 当根据栅极第一HKMG方法形成场效应晶体管时，形成在栅电极顶部上的覆盖层必须在硅化步骤之前去除，导致在栅电极的表面上形成金属硅化物层，并且 晶体管的源极和漏极区域。 本公开通过跳过栅极盖去除工艺来改善制造流程。 仅在源区和漏区形成金属硅化物。 然后通过形成通过栅极材料的孔而使栅电极接触，留下栅极金属层的表面。

公开(公告)号：US09412848B1

公开(公告)日：2016-08-09

申请号：US14615529

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66772 ,  H01L29/78696

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract translation: 本公开提供了形成半导体器件和半导体器件的方法。 提供具有半导体层，掩埋绝缘材料层和体基板的SOI衬底部分，其中埋入绝缘材料层插入在半导体层和块状衬底之间。 SOI衬底部分随后被图案化以便在本体衬底上形成图案化的双层堆叠，该双层堆叠包括图案化的半导体层和图案化的掩埋绝缘材料层。 双层堆叠进一步被另外的绝缘材料层封闭，并且在另外的绝缘材料层上和周围形成电极材料。 这里，栅电极由体基板和电极材料形成，使得栅电极基本上围绕由图案化的掩埋绝缘材料层的一部分形成的沟道部分。

公开(公告)号：US20160204217A1

公开(公告)日：2016-07-14

申请号：US15076895

申请日：2016-03-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/161 ,  H01L29/78 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor product with certain devices having a first device with a fully silicided (FuSi) gate and a second device with a partially silicided gate is disclosed. In one example, the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed above a layer of polysilicon or amorphous silicon during the silicidation process.

Abstract translation: 具有某些器件的半导体产品具有具有完全硅化（FuSi）栅极的第一器件和具有部分硅化栅极的第二器件。 在一个示例中，第一半导体器件凹入，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅电极材料上，在硅化处理期间，在多晶硅层或非晶硅层之上形成硅化物部分。