Invention Grant
US09015396B2 Reducing latency in a peripheral component interconnect express link 有权
减少外设组件互连中的延迟快速链接

Reducing latency in a peripheral component interconnect express link
Abstract:
A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.
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