Invention Grant
- Patent Title: Reducing latency in a peripheral component interconnect express link
- Patent Title (中): 减少外设组件互连中的延迟快速链接
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Application No.: US13622266Application Date: 2012-09-18
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Publication No.: US09015396B2Publication Date: 2015-04-21
- Inventor: Michael W. Murphy , Joshua P. de Cesare , Timothy R. Paaske
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Agent A. Richard Park
- Main IPC: G06F13/24
- IPC: G06F13/24 ; G06F1/32 ; G06F1/00

Abstract:
A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.
Public/Granted literature
- US20140082242A1 REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK Public/Granted day:2014-03-20
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