Invention Grant
- Patent Title: Method of making a 3D integrated circuit
- Patent Title (中): 制作3D集成电路的方法
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Application No.: US13751489Application Date: 2013-01-28
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Publication No.: US09018078B2Publication Date: 2015-04-28
- Inventor: Benoit Sklenard , Perrine Batude
- Applicant: STMicroelectronics S.A. , Commissariat à l'Énergie Atomique et aux Énergies Alternatives
- Applicant Address: FR Montrouge FR Paris
- Assignee: STMicroelectronics SA,Commissariat a l'Energie Atomique et aux Energies Alternatives
- Current Assignee: STMicroelectronics SA,Commissariat a l'Energie Atomique et aux Energies Alternatives
- Current Assignee Address: FR Montrouge FR Paris
- Agency: Gardere Wynne Sewell LLP
- Priority: FR1250950 20120201
- Main IPC: H01L21/46
- IPC: H01L21/46 ; H01L23/58 ; H01L21/02 ; H01L27/06 ; H01L27/12 ; H01L21/822
Abstract:
A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.
Public/Granted literature
- US20130193550A1 3D INTEGRATED CIRCUIT Public/Granted day:2013-08-01
Information query
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