Invention Grant
US09018085B2 Method of fabricating memory device with charge storage layer at gap located side of gate dielectric underneath the gate
有权
在栅极下方的栅极电介质的间隙位置制造具有电荷存储层的存储器件的方法
- Patent Title: Method of fabricating memory device with charge storage layer at gap located side of gate dielectric underneath the gate
- Patent Title (中): 在栅极下方的栅极电介质的间隙位置制造具有电荷存储层的存储器件的方法
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Application No.: US14198320Application Date: 2014-03-05
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Publication No.: US09018085B2Publication Date: 2015-04-28
- Inventor: Shih-Guei Yan , Wen-Jer Tsai , Cheng-Hsien Cheng
- Applicant: MACRONIX International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX International Co., Ltd.
- Current Assignee: MACRONIX International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: J.C. Patents
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/28 ; H01L29/423 ; H01L29/788 ; H01L29/792 ; H01L27/115
Abstract:
A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.
Public/Granted literature
- US20140187032A1 METHOD FOR FABRICATING MEMORY DEVICE Public/Granted day:2014-07-03
Information query
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