Invention Grant
US09041139B2 Low voltage diode with reduced parasitic resistance and method for fabricating 有权
降低寄生电阻的低压二极管和制造方法

Low voltage diode with reduced parasitic resistance and method for fabricating
Abstract:
A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n−, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal; and an ohmic contact is deposited on the n+ layer.
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