公开(公告)号：US09450081B2

公开(公告)日：2016-09-20

申请号：US14709211

申请日：2015-05-11

Applicant: CREE, INC.

Inventor： Yifeng Wu ,  Primit Parikh ,  Umesh Mishra

IPC: H01L29/76 ,  H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7786

Abstract: A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.

Abstract translation: 多场板晶体管包括有源区，源极，漏极和栅极。 第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。 第一间隔层上的第一场板连接到栅极。 第二间隔层上的第二场板连接到栅极。 第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。 晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，导通电阻不超过5.0mΩ-cm 2，至少为600伏特，同时支持至少3安培的电流， 电阻不大于5.3mΩ-cm 2，至少900V，同时支持至少2安培的电流，导通电阻不大于6.6mΩ-cm 2，或阻塞电压至少为900V，同时支持电流 至少3安培，导通电阻不大于7.0mΩ-cm2。

公开(公告)号：US11664429B2

公开(公告)日：2023-05-30

申请号：US15696050

申请日：2017-09-05

Applicant: CREE, INC.

Inventor： Yifeng Wu ,  Primit Parikh ,  Umesh Mishra ,  Marcia Moore

IPC: H01L29/812 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/402 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/812 ,  H01L29/2003

Abstract: A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the device.

公开(公告)号：US20170365670A1

公开(公告)日：2017-12-21

申请号：US15696050

申请日：2017-09-05

Applicant: CREE, INC.

Inventor： Yifeng Wu ,  Primit Parikh ,  Umesh Mishra ,  Marcia Moore

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/812 ,  H01L29/20

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/812

Abstract: A field effect transistor comprising a buffer and channel layer formed successively on a substrate. A source electrode, drain electrode, and gate are all formed in electrical contact with the channel layer, with the gate between the source and drain electrodes. A spacer layer is formed on at least a portion of a surface of the channel layer between the gate and drain electrode and a field plate is formed on the spacer layer isolated from the gate and channel layer. The spacer layer is electrically connected by at least one conductive path to the source electrode, wherein the field plate reduces the peak operating electric field in the device.

公开(公告)号：US09041139B2

公开(公告)日：2015-05-26

申请号：US13693929

申请日：2012-12-04

Applicant: CREE, INC.

Inventor： Primit Parikh ,  Sten Heikman

IPC: H01L29/66 ,  H01L29/47 ,  H01L29/872 ,  H01L29/20

CPC classification number: H01L29/66143 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66212 ,  H01L29/872

Abstract: A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n−, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal; and an ohmic contact is deposited on the n+ layer.

Abstract translation: 制造二极管的方法开始于在SiC衬底上沉积Al x Ga 1-x N成核层，然后沉积n + GaN缓冲层，n-GaN层，Al x Ga 1-x N势垒层和SiO 2电介质层。 去除介电层的一部分并沉积在空隙中的肖特基金属。 使用Au-Sn结晶晶片接合工艺用金属接合层将电介质层固定到支撑层上，使用反应离子蚀刻去除衬底以露出n +层，n +，n-和阻挡层的选定部分 被去除以在肖特基金属上的介电层上形成台面二极管结构; 并且在n +层上沉积欧姆接触。

公开(公告)号：US20160035870A1

公开(公告)日：2016-02-04

申请号：US14709211

申请日：2015-05-11

Applicant: CREE, INC.

Inventor： Yifeng Wu ,  Primit Parikh ,  Umesh Mishra

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7786

Abstract: A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.

Abstract translation: 多场板晶体管包括有源区，源极，漏极和栅极。 第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。 第一间隔层上的第一场板连接到栅极。 第二间隔层上的第二场板连接到栅极。 第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。 晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，其导通电阻不超过5.0mΩ（OHgr·-cm2）为至少600伏，同时支持至少3安培的电流 耐电压不超过5.3mΩ，OHgr--cm2，至少900V，同时支持至少2安培的电流，导通电阻不超过6.6mΩ，OHgr-cm2，或阻断电压至少为900V，同时 支持至少3安培的电流，导通电阻不超过7.0mΩ，OHgr; -cm2。

公开(公告)号：US09226383B2

公开(公告)日：2015-12-29

申请号：US14338686

申请日：2014-07-23

Applicant: CREE, INC.

Inventor： Umesh Mishra ,  Primit Parikh ,  Yifeng Wu

IPC: H01L29/00 ,  H01L23/34 ,  H01L23/48 ,  H05K1/02 ,  H01L21/8252 ,  H01L23/66 ,  H01L27/06 ,  H05K1/18 ,  H01L23/14 ,  H01L23/367 ,  H01L29/20 ,  H01L29/778

CPC classification number: H05K1/0206 ,  H01L21/8252 ,  H01L23/147 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/66 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/73253 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/181 ,  H05K2201/066 ,  Y10T29/4913 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.

Abstract translation: 电路基板在第一表面上具有一个或多个有源部件和多个无源电路元件。 有源半导体器件具有材料层和多个端子的衬底。 有源半导体器件被倒装芯片安装在电路基板上，并且器件的至少一个端子与电路基板上的有源元件电连接。 基板上的有源元件和安装有倒装芯片的有源半导体器件与无源电路元件组合形成前置放大器和输出放大器。 在电源开关配置中，电路基板在第一表面上具有逻辑控制电路。 安装在电路基板上的半导体晶体管倒装芯片电连接到第一表面上的控制电路，从而控制倒装芯片安装器件的接通和断开。

公开(公告)号：US09224596B2

公开(公告)日：2015-12-29

申请号：US13975491

申请日：2013-08-26

Applicant: Cree, Inc.

Inventor： Adam William Saxler ,  Yifeng Wu ,  Primit Parikh ,  Umesh Mishra ,  Richard Peter Smith ,  Scott T. Sheppard

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/36 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02425 ,  H01L21/02439 ,  H01L21/02491 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7787

Abstract: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.

Abstract translation: 提供半导体器件结构和制造半导体器件结构的方法，其包括在导电半导体衬底和/或导电层上的半绝缘或绝缘GaN外延层。 半绝缘或绝缘的GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括在导电SiC衬底上的导电SiC衬底和绝缘或半绝缘GaN外延层。 GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括导电GaN衬底，导电GaN衬底上的绝缘或半绝缘GaN外延层，GaN外延层上的GaN基半导体器件和 通孔和通孔中相应的通孔金属延伸穿过GaN基半导体器件和GaN外延层的层。

公开(公告)号：US20130344687A1

公开(公告)日：2013-12-26

申请号：US13975491

申请日：2013-08-26

Applicant: Cree, Inc.

Inventor： Adam William Saxler ,  Yifeng Wu ,  Primit Parikh ,  Umesh Mishra ,  Richard Peter Smith ,  Scott T. Sheppard

IPC: H01L21/02

CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02425 ,  H01L21/02439 ,  H01L21/02491 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7787

Abstract: Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.

Abstract translation: 提供半导体器件结构和制造半导体器件结构的方法，其包括在导电半导体衬底和/或导电层上的半绝缘或绝缘GaN外延层。 半绝缘或绝缘GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括在导电SiC衬底上的导电SiC衬底和绝缘或半绝缘GaN外延层。 GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括导电GaN衬底，导电GaN衬底上的绝缘或半绝缘GaN外延层，GaN外延层上的GaN基半导体器件和 通孔和通孔中相应的通孔金属延伸穿过GaN基半导体器件和GaN外延层的层。

公开(公告)号：US20130126894A1

公开(公告)日：2013-05-23

申请号：US13693929

申请日：2012-12-04

Applicant: CREE, INC.

Inventor： Primit Parikh ,  Sten Heikman

IPC: H01L29/66 ,  H01L29/872

CPC classification number: H01L29/66143 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66212 ,  H01L29/872

Abstract: A method of making a diode begins by depositing an AlxGa1-xN nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an AlxGa1-xN barrier layer, and an SiO2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n−, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal; and an ohmic contact is deposited on the n+ layer.

Abstract translation: 制造二极管的方法开始于在SiC衬底上沉积Al x Ga 1-x N成核层，然后沉积n + GaN缓冲层，n-GaN层，Al x Ga 1-x N势垒层和SiO 2电介质层。 去除介电层的一部分并沉积在空隙中的肖特基金属。 使用Au-Sn结晶晶片接合工艺用金属接合层将电介质层固定到支撑层上，使用反应离子蚀刻去除衬底以露出n +层，n +，n-和阻挡层的选定部分 被去除以在肖特基金属上的介电层上形成台面二极管结构; 并且在n +层上沉积欧姆接触。