Invention Grant
US09041444B1 Time-to-digital convertor-assisted phase-locked loop spur mitigation 有权
时间 - 数字转换器辅助锁相环刺激减轻

Time-to-digital convertor-assisted phase-locked loop spur mitigation
Abstract:
Methods, systems, and apparatuses are described for compensating for an undesired fractional spur due to a PLL in a communication system. The communication system includes a time-to-digital converter (TDC) that is configured to execute in parallel to the PLL. The TDC is configured to determine a phase difference between a reference frequency and an output oscillation signal provided by the PLL. The phase difference is received by a processor to estimate particular characteristics of the undesired fractional spur, and the estimate of the characteristics is used to construct an estimate of the undesired fractional spur.
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