Invention Grant
- Patent Title: Banking of reliability metrics
- Patent Title (中): 可靠性指标银行
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Application No.: US13729400Application Date: 2012-12-28
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Publication No.: US09043659B2Publication Date: 2015-05-26
- Inventor: Enric Herrero Abellanas , Xavier Vera , Javier Carretero Casado , Tanausu Ramirez , Nicholas Axelos , Daniel Sanchez
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.
Public/Granted literature
- US20140189439A1 BANKING OF RELIABILITY METRICS Public/Granted day:2014-07-03
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