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    Selective provision of error correction for memory
    2.
    发明授权
    Selective provision of error correction for memory 有权
    选择性地提供存储器的纠错

    公开(公告)号：US09071281B2

    公开(公告)日：2015-06-30

    申请号：US13792117

    申请日：2013-03-10

    Applicant: Intel Corporation

    Inventor： Javier Carretero Casado ,  Xavier Vera ,  Daniel Sanchez ,  Tanausu Ramirez ,  Enric Herrero Abellanas ,  Nicholas Axelos

    IPC: H03M13/00 ,  H03M13/35

    CPC classification number: H03M13/35 ,  G06F11/1012

    Abstract: Embodiments of apparatuses, methods, and storage medium associated with selectively providing error correction to memory are disclosed herein. In one instance, an apparatus may include a memory controller configured to control access to a non-volatile memory having storage locations. The controller may be configured to provide a first error correction arrangement to provide a first level of error correction capability for data stored in the non-volatile memory. The memory controller may include a control/error correction block configured to provide a second error correction arrangement with a second level of error correction capability for data stored in the non-volatile memory. The second level of error correction capability enables correction of at least one bit error more than the first level. The memory controller may be configured to selectively employ the second error correction arrangement to complement the first error correction arrangement. Other embodiments may be described and claimed.

    Abstract translation: 本文公开了与选择性地向存储器提供错误校正相关联的装置，方法和存储介质的实施例。 在一种情况下，装置可以包括被配置为控制对具有存储位置的非易失性存储器的访问的存储器控​​制器。 控制器可以被配置为提供第一纠错装置，以便为存储在非易失性存储器中的数据提供第一级的纠错能力。 存储器控制器可以包括控制/错误校正块，其被配置为向存储在非易失性存储器中的数据提供具有第二级纠错能力的第二纠错装置。 第二级的纠错能力能够比第一级别更正至少一位误差。 存储器控制器可以被配置为选择性地使用第二纠错装置来补充第一纠错装置。 可以描述和要求保护其他实施例。

    VULNERABILITY ESTIMATION FOR CACHE MEMORY
    4.
    发明申请
    VULNERABILITY ESTIMATION FOR CACHE MEMORY 有权
    缓存记忆的易损性估计

    公开(公告)号：US20140281740A1

    公开(公告)日：2014-09-18

    申请号：US13976285

    申请日：2013-03-13

    Applicant: Intel Corporation

    Inventor： Javier Carretero Casado ,  Xavier Vera ,  Tanausu Ramirez ,  Daniel Sanchez ,  Enric Herrero Abellanas ,  Nicholas Axelos

    IPC: G06F11/34

    CPC classification number: G06F11/3409 ,  G06F11/3471 ,  G06F2201/88 ,  G06F2201/885

    Abstract: A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole.

    Abstract translation: 确定高速缓存存储器的脆弱性的方法包括将第一计数器与高速缓存元件相关联并且周期性地增加第一计数器。 当消耗高速缓存元件中的数据的读取或其他访问发生时，累积第一计数器的当前值。 当发生修改高速缓存元件中的数据的写入或其他高速缓存访​​问时，第一个计数器被复位。 在评估期结束时，总计数器中的值近似于所消耗的数据易受攻击的时钟周期数。 将该值除以时钟周期的数量将近似该缓存元素的漏洞。 所有高速缓存元素的子集的漏洞可以被测量和外插，以获得对整个高速缓冲存储器的脆弱性的估计。

    Vulnerability estimation for cache memory
    5.
    发明授权
    Vulnerability estimation for cache memory 有权
    高速缓存的漏洞估计

    公开(公告)号：US09075904B2

    公开(公告)日：2015-07-07

    申请号：US13976285

    申请日：2013-03-13

    Applicant: Intel Corporation

    Inventor： Javier Carretero Casado ,  Xavier Vera ,  Tanausu Ramirez ,  Daniel Sanchez ,  Enric Herrero Abellanas ,  Nicholas Axelos

    IPC: G06F11/34

    CPC classification number: G06F11/3409 ,  G06F11/3471 ,  G06F2201/88 ,  G06F2201/885

    Abstract: A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole.

    Abstract translation: 确定高速缓存存储器的脆弱性的方法包括将第一计数器与高速缓存元件相关联并且周期性地增加第一计数器。 当消耗高速缓存元件中的数据的读取或其他访问发生时，累积第一计数器的当前值。 当发生修改高速缓存元件中的数据的写入或其他高速缓存访​​问时，第一个计数器被复位。 在评估期结束时，总计数器中的值近似于所消耗的数据易受攻击的时钟周期数。 将该值除以时钟周期的数量将近似该缓存元素的漏洞。 所有高速缓存元素的子集的漏洞可以被测量和外插，以获得对整个高速缓冲存储器的脆弱性的估计。

    Banking of reliability metrics
    6.
    发明授权
    Banking of reliability metrics 有权
    可靠性指标银行

    公开(公告)号：US09043659B2

    公开(公告)日：2015-05-26

    申请号：US13729400

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Enric Herrero Abellanas ,  Xavier Vera ,  Javier Carretero Casado ,  Tanausu Ramirez ,  Nicholas Axelos ,  Daniel Sanchez

    IPC: G06F11/00

    CPC classification number: G06F11/008

    Abstract: In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括至少一个功能块和银行逻辑。 银行业务逻辑可以是确定与至少一个功能块相关联的平均可靠性度量。 如果平均可靠性度量超过所需等级，则银行业务逻辑也可以是在所述至少一个功能块中实现降低的可靠性模式，其中所述降低的可靠性模式与平均可靠性度量的降低相关联。 描述和要求保护其他实施例。

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