Invention Grant
- Patent Title: Molded glass lid for wafer level packaging of opto-electronic assemblies
- Patent Title (中): 用于光电组件晶圆级封装的成型玻璃盖
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Application No.: US13656528Application Date: 2012-10-19
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Publication No.: US09052445B2Publication Date: 2015-06-09
- Inventor: Kishor Desai , Ravinder Kachru , Vipulkumar Patel , Bipin Dama , Kalpendu Shastri , Soham Pathak
- Applicant: Cisco Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: CISCO Technology, Inc.
- Current Assignee: CISCO Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Patterson & Sheridan LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; G02B6/12 ; H01L33/52 ; G02B6/42 ; G02B6/43 ; H01L23/04 ; H01L23/48 ; H01L25/16 ; H01L31/0203 ; H05K1/02 ; H01L21/50

Abstract:
An opto-electronic assembly is provided comprising a substrate (generally of silicon or glass) for supporting a plurality of interconnected optical and electrical components. A layer of sealing material is disposed to outline a defined peripheral area of the substrate. A molded glass lid is disposed over and bonded to the substrate, where the molded glass lid is configured to create a footprint that matches the defined peripheral area of the substrate. The bottom surface of the molded glass lid includes a layer of bonding material that contacts the substrate's layer of sealing material upon contact, creating a bonded assembly. In one form, a wafer level assembly process is proposed where multiple opto-electronic assemblies are disposed on a silicon wafer and multiple glass lids are molded in a single sheet of glass that is thereafter bonded to the silicon wafer.
Public/Granted literature
- US20130101250A1 Molded Glass Lid For Wafer Level Packaging Of Opto-Electronic Assemblies Public/Granted day:2013-04-25
Information query
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