Invention Grant
US09052947B2 Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
有权
统一的乐观和悲观的并发控制软件事务内存（STM）系统
- Patent Title: Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
- Patent Title (中): 统一的乐观和悲观的并发控制软件事务内存（STM）系统
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Application No.: US14028018Application Date: 2013-09-16
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Publication No.: US09052947B2Publication Date: 2015-06-09
- Inventor: Ali-Reza Adl-Tabatabai , Moshe Bach , Sion Berkowits , James Henry Cownie , Yang Ni , Jeffrey V. Olivier , Bratin Saha , Ady Tal , Adam Welc
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Barnes & Thornburg LLP
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F17/30 ; G06F9/52
Abstract:
A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
Public/Granted literature
- US20140156953A1 Unified Optimistic and Pessimistic Concurrency Control for a Software Transactional Memory (STM) System Public/Granted day:2014-06-05
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