公开(公告)号：US09304769B2

公开(公告)日：2016-04-05

申请号：US14271024

申请日：2014-05-06

Applicant: Intel Corporation

Inventor： Bratin Saha ,  Ali-Reza Adl-Tabatabai ,  Quinn A. Jacobson

IPC: G06F9/45 ,  G06F13/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F12/08

CPC classification number: G06F9/30087 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/467 ,  G06F12/0837 ,  G06F2212/62

Abstract: A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries. Furthermore, new versions of newly compiled functions may be inserted to provide strong atomicity between previously and newly compiled functions.

Abstract translation: 这里描述了使用预编译二进制文件实现软件事务存储器（STM）的方法和装置。 在事务中遇到访问操作时，检查与由访问引用的存储器位置相关联的注释字段。 响应于表示事务内先前类似访问的存储器位置，访问被执行而没有访问障碍。 然而，如果注释字段处于表示在事务的挂起期间没有先前访问的默认状态，则确定处理器的模式。 如果处理器模式处于隐式模式，则异步执行访问处理程序/障碍。 相反，在显式模式下，设置标志而不是异步执行处理程序。 此外，在编译期间，转换显式和转换隐式指令将被智能地转换为预编译和新编译的二进制文件的模式。 此外，可以插入新版本的新编译的函数，以便在先前和新编译的函数之间提供强大的原子性。

公开(公告)号：US08997114B2

公开(公告)日：2015-03-31

申请号：US14173071

申请日：2014-02-05

Applicant: Intel Corporation

Inventor： Xiaocheng Zhou ,  Shoumeng Yan ,  Ying Gao ,  Hu Chen ,  Peinan Zhang ,  Mohan Rajagopalan ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/44 ,  G06F13/14 ,  G06F13/00 ,  G06T1/60 ,  G06F9/54 ,  G06F12/10

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

Abstract translation: 本发明的实施例为CPU-GPU平台提供语言支持。 在一个实施例中，可以在CPU和GPU两者上灵活地执行代码。 CPU代码可以将内核卸载到GPU。 该内核可能会调用CPU上的预先存在的库，或者调用其他CPU函数。 这允许构建应用程序，而不需要重新编译整个调用链。 此外，在一个实施例中，数据可以在CPU和GPU之间无缝共享。 这包括共享可能具有虚拟功能的对象。 因此，如果CPU或GPU调用虚拟功能，这些实施例可以确保在CPU或GPU上调用正确的虚拟功能。

公开(公告)号：US08856466B2

公开(公告)日：2014-10-07

申请号：US13658360

申请日：2012-10-23

Applicant: Intel Corporation

Inventor： Ali-Reza Adl-Tabatabai ,  Yang Ni ,  Bratin Saha ,  Vadim Bassin ,  Gad Sheaffer ,  David Callahan ,  Jan Gray

IPC: G06F12/16

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在第一线程中执行事务性存储器（TM）事务的方法，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块，并且获取所述块上的写监视器 在第一缓冲器中的块的位置处的数据被更新的遇到时间获得块的所有权。 描述和要求保护其他实施例。

公开(公告)号：US09195600B2

公开(公告)日：2015-11-24

申请号：US14536805

申请日：2014-11-10

Applicant: Intel Corporation

Inventor： Ali-Reza Adl-Tabatabai ,  Yang Ni ,  Bratin Saha ,  Vadim Bassin ,  Gad Sheaffer ,  David Callahan ,  Jan Gray

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F12/10 ,  G06F9/30

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在第一线程中执行事务性存储器（TM）事务的方法，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块，并且获取所述块上的写监视器 在第一缓冲器中的块的位置处的数据被更新的遇到时间获得块的所有权。 描述和要求保护其他实施例。

公开(公告)号：US09052947B2

公开(公告)日：2015-06-09

申请号：US14028018

申请日：2013-09-16

Applicant: Intel Corporation

Inventor： Ali-Reza Adl-Tabatabai ,  Moshe Bach ,  Sion Berkowits ,  James Henry Cownie ,  Yang Ni ,  Jeffrey V. Olivier ,  Bratin Saha ,  Ady Tal ,  Adam Welc

IPC: G06F9/46 ,  G06F17/30 ,  G06F9/52

CPC classification number: G06F9/467 ,  G06F9/528 ,  G06F17/30351 ,  G06F17/30353 ,  G06F17/30356 ,  G06F17/30359

Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

Abstract translation: 这里描述了用于软件事务存储器（STM）中的统一并发控制的方法和装置。 与由事务性存储器访问操作引用的存储器地址相关联的事务记录包括乐观和悲观的并发控制字段。 利用访问障碍和其他交易操作/功能来适当地维护交易记录的两个领域。 因此，同时执行乐观和悲观的交易得以实现。

公开(公告)号：US09733937B2

公开(公告)日：2017-08-15

申请号：US13843305

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Bratin Saha ,  Matthew C. Merten ,  Per Hammarlund

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

Abstract: A method, apparatus, and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.

公开(公告)号：US10229256B2

公开(公告)日：2019-03-12

申请号：US14129790

申请日：2013-10-25

Applicant: Intel Corporation

Inventor： Karthik K. Rishi ,  Bratin Saha

IPC: G06F21/00 ,  G06F21/32 ,  G06F21/34 ,  G06F21/31 ,  H04L29/06

Abstract: Technologies for authenticated audio login by a user of a computing device include generating a security token having a plurality of token characters. The computing device renders the generated security token to a current user of the computing device on an output device of the computing device. The computing device, receives security token audio input from the current user and retrieves, based on the rendered security token, voice profile data of an authorized user of the computing device from a voice profile database. The voice profile database includes voice data based on the authorized user's prior recitation of each token character of a set of token characters from which the security token may be composed. The computing device compares the received security token audio input and the retrieved voice profile data to verify that the current user is the authenticated user and the current user recited the rendered security token.

公开(公告)号：US09400702B2

公开(公告)日：2016-07-26

申请号：US14320985

申请日：2014-07-01

Applicant: Intel Corporation

Inventor： Hu Chen ,  Ying Gao ,  Xiaocheng Zhou ,  Shoumeng Yan ,  Peinan Zhang ,  Mohan Rajagopalan ,  Jesse Fang ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/54 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

公开(公告)号：US20150113255A1

公开(公告)日：2015-04-23

申请号：US14569454

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Shoumeng Yan ,  Xiaocheng Zhou ,  Hu Chen ,  Ying Gao ,  Sai Luo ,  Bratin Saha

IPC: G06F12/10 ,  G06F9/38

CPC classification number: G06F12/1072 ,  G06F8/447 ,  G06F9/3863 ,  G06F9/3885 ,  G06F9/548 ,  G06F2212/657

Abstract: A computing platform may include heterogeneous processors (e.g., CPU and a GPU) to support sharing of virtual functions between such processors. In one embodiment, a CPU side vtable pointer used to access a shared object from the CPU 110 may be used to determine a GPU vtable if a GPU-side table exists. In another embodiment, a shared non-coherent region, which may not maintain data consistency, may be created within the shared virtual memory. The CPU and the GPU side data stored within the shared non-coherent region may have a same address as seen from the CPU and the GPU side. However, the contents of the CPU-side data may be different from that of GPU-side data as shared virtual memory may not maintain coherency during the run-time. In one embodiment, the vptr may be modified to point to the CPU vtable and GPU vtable stored in the shared virtual memory.

Abstract translation: 计算平台可以包括异构处理器（例如，CPU和GPU），以支持这些处理器之间的虚拟功能的共享。 在一个实施例中，如果GPU侧表存在，则用于从CPU 110访问共享对象的CPU侧vtable指针可用于确定GPU vtable。 在另一个实施例中，可以在共享虚拟存储器内创建可能不维持数据一致性的共享非相干区域。 存储在共享非相干区域内的CP​​U和GPU侧数据可以具有与CPU和GPU侧所见相同的地址。 然而，CPU侧数据的内容可能与GPU侧数据的内容不同，因为共享虚拟存储器可能在运行期间不能维持一致性。 在一个实施例中，可以修改vptr以指向存储在共享虚拟存储器中的CPU vtable和GPU vtable。

公开(公告)号：US08886894B2

公开(公告)日：2014-11-11

申请号：US13658264

申请日：2012-10-23

Applicant: Intel Corporation

Inventor： Ali-Reza Adl-Tabatabai ,  Yang Ni ,  Bratin Saha ,  Vadim Bassin ,  Gad Sheaffer ,  David Callahan ,  Jan Gray

IPC: G06F12/16

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.