发明授权
US09064770B2 Methods for minimizing edge peeling in the manufacturing of BSI chips
有权
BSI芯片制造中边缘剥离最小化的方法
- 专利标题： Methods for minimizing edge peeling in the manufacturing of BSI chips
- 专利标题（中）： BSI芯片制造中边缘剥离最小化的方法
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申请号： US13551457申请日： 2012-07-17
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公开(公告)号： US09064770B2公开(公告)日： 2015-06-23
- 发明人: Chun-Ting Kuo , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
- 申请人： Chun-Ting Kuo , Kei-Wei Chen , Ying-Lang Wang , Kuo-Hsiu Wei
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Slater & Matsil, L.L.P.
- 主分类号： H01L21/02
- IPC分类号： H01L21/02 ; H01L27/146
摘要：
A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.
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