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156 条记录 (耗时 0.022 秒)

    Modular grinding apparatuses and methods for wafer thinning
    2.
    发明授权
    Modular grinding apparatuses and methods for wafer thinning 有权
    用于晶片薄化的模块化研磨装置和方法

    公开(公告)号：US09570311B2

    公开(公告)日：2017-02-14

    申请号：US13370946

    申请日：2012-02-10

    申请人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    发明人： Chun-Ting Kuo ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Kuo-Hsiu Wei

    IPC分类号： H01L21/304 ,  B24B37/04 ,  B24B37/00

    CPC分类号： H01L21/304 ,  B24B37/00 ,  B24B37/042

    摘要： Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.

    摘要翻译： 公开了使多个半导体晶片变薄的方法及其实施方法。 一组研磨模块内的研磨模块接收并研磨半导体晶片。 抛光模块从研磨模块接收半导体晶片并抛光晶片。 抛光模块被配置为在比研磨模块构造成磨碎相应晶片的时间少的时间内抛光半导体晶片。

    BSI image sensor chips and methods for forming the same
    4.
    发明授权
    BSI image sensor chips and methods for forming the same 有权
    BSI图像传感器芯片及其形成方法

    公开(公告)号：US09356059B2

    公开(公告)日：2016-05-31

    申请号：US13352980

    申请日：2012-01-18

    申请人： Shiu-Ko JangJian ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Shiu-Ko JangJian ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L29/04 ,  H01L27/146

    CPC分类号： H01L27/14623 ,  H01L27/1464 ,  H01L27/14685

    摘要： A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.

    摘要翻译： 一种器件包括具有正面和背面的半导体衬底。 多晶硅层设置在半导体衬底的背面。 多晶硅层包括掺杂有p型杂质的部分。 电介质层设置在半导体衬底的背面，其中多晶硅层位于半导体衬底和多晶硅层之间。

    Methods and apparatus for an improved reflectivity optical grid for image sensors
    6.
    发明授权
    Methods and apparatus for an improved reflectivity optical grid for image sensors 有权
    用于图像传感器的改进的反射率光栅的方法和装置

    公开(公告)号：US08890273B2

    公开(公告)日：2014-11-18

    申请号：US13363280

    申请日：2012-01-31

    申请人： Shiu-Ko JangJian ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Shiu-Ko JangJian ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L31/00 ,  H01L31/0224

    CPC分类号： H01L31/022441 ,  H01L27/14623 ,  H01L27/14629 ,  H01L27/1464 ,  H01L31/022433

    摘要： An improved reflectivity optical grid for image sensors. In an embodiment, a backside illuminated CIS device includes a semiconductor substrate having a pixel array area comprising a plurality of photosensors formed on a front side surface of the semiconductor substrate, each of the photosensors forming a pixel in the pixel array area; an optical grid material disposed over a backside surface of the semiconductor substrate, the optical grid material patterned to form an optical grid that bounds each of the pixels in the pixel array area and extending above the semiconductor substrate, the optical grid having sidewalls and a top portion; and a highly reflective coating formed over the optical grid, comprising a pure metal coating of a metal that is at least 99% pure, and a high-k dielectric coating over the pure metal coating that has a refractive index of greater than about 2.0. Methods are also disclosed.

    摘要翻译： 用于图像传感器的改进的反射光栅。 在一个实施例中，背面照明的CIS器件包括具有像素阵列区域的半导体衬底，该像素阵列区域包括形成在半导体衬底的前侧表面上的多个光电传感器，每个光电传感器在像素阵列区域中形成像素; 设置在半导体衬底的背侧表面上的光栅格材料，所述光栅格材料被图案化以形成限定像素阵列区域中的每个像素并在半导体衬底上方延伸的光栅，所述光栅具有侧壁和顶部 一部分; 以及形成在光栅上的高反射涂层，包括纯金属的纯金属涂层，其纯度至少为99％，纯金属涂层上的高k电介质涂层具有大于约2.0的折射率。 还公开了方法。

    Image Sensor Manufacturing Methods
    7.
    发明申请
    Image Sensor Manufacturing Methods 有权
    图像传感器制造方法

    公开(公告)号：US20130273686A1

    公开(公告)日：2013-10-17

    申请号：US13445766

    申请日：2012-04-12

    申请人： Mu-Han Cheng ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Mu-Han Cheng ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L31/0232 ,  H01L21/28

    CPC分类号： H01L27/14623 ,  H01L27/1464 ,  H01L27/14687

    摘要： Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process.

    摘要翻译： 公开了半导体器件和背面照明（BSI）传感器制造方法。 在一个实施例中，制造半导体器件的方法包括提供工件并在工件的前侧形成集成电路。 使用镶嵌工艺在工件的背面上形成导电材料的格栅。

    Methods and Apparatus for Resistive Random Access Memory (RRAM)
    8.
    发明申请
    Methods and Apparatus for Resistive Random Access Memory (RRAM) 有权
    电阻随机存取存储器（RRAM）的方法和装置

    公开(公告)号：US20130234094A1

    公开(公告)日：2013-09-12

    申请号：US13416183

    申请日：2012-03-09

    申请人： Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

    发明人： Ting-Chang Chang ,  Yong-En Syu ,  Fu-Yen Jian ,  Shih-Chieh Chang ,  Ying-Lang Wang

    IPC分类号： H01L45/00

    CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/145 ,  H01L45/1608

    摘要： Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

    摘要翻译： 公开了一种用于电阻随机存取存储器（RRAM）装置的方法和装置。 RRAM器件包括底电极，设置在底电极上的电阻开关层和设置在电阻开关层上的顶电极。 电阻开关层由金属，Si和O的复合材料制成。在顶部电极和底部电极之间可能存在额外的隧道势垒层。 顶部电极和底部电极可以包括多个子层。

    Semiconductor device contact structures and methods for making the same
    9.
    发明授权
    Semiconductor device contact structures and methods for making the same 有权
    半导体器件接触结构及其制造方法

    公开(公告)号：US08518819B2

    公开(公告)日：2013-08-27

    申请号：US13049049

    申请日：2011-03-16

    申请人： Shih Chieh Chang ,  Chih-Chung Chang ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Shih Chieh Chang ,  Chih-Chung Chang ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L23/53266 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.

    摘要翻译： 半导体接触结构和方法提供延伸穿过电介质材料并提供与包括硅化物材料和非硅化物材料（例如掺杂硅）的多个不同下层材料的接触的接触结构。 接触结构包括使用多步电离金属等离子体（IMP）沉积操作形成的下复合层。 下部IMP膜以高AC偏压功率形成，随后以较低的AC偏压功率形成上部IMP膜。 复合层可以由钛形成。 在复合层上形成另一层作为衬垫，并且衬垫层可以有利地使用CVD形成，并且可以是TiN。 诸如钨或铜的导电插塞材料填充接触开口。

    WAFER THINNING APPARATUS HAVING FEEDBACK CONTROL AND METHOD OF USING
    10.
    发明申请
    WAFER THINNING APPARATUS HAVING FEEDBACK CONTROL AND METHOD OF USING 审中-公开
    具有反馈控制功能的减速装置和使用方法

    公开(公告)号：US20130210172A1

    公开(公告)日：2013-08-15

    申请号：US13371046

    申请日：2012-02-10

    申请人： Yuan-Hsuan Chen ,  Kei-Wei CHEN ,  Ying-Lang WANG ,  Kuo-Hsiu WEI

    发明人： Yuan-Hsuan Chen ,  Kei-Wei CHEN ,  Ying-Lang WANG ,  Kuo-Hsiu WEI

    IPC分类号： H01L21/66 ,  B24B49/00 ,  H01L21/306

    CPC分类号： H01L21/30625 ,  B24B37/005 ,  B24B37/04 ,  B24B49/00 ,  B24B49/04 ,  B24B49/05 ,  H01L21/304 ,  H01L22/12 ,  H01L22/20

    摘要： A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time.

    摘要翻译： 晶片减薄装置包括被配置为测量晶片的初始厚度的第一计量工具。 晶片减薄装置还包括连接到第一计量工具的控制器，并且被配置为基于初始厚度，预定厚度和材料移除速率来确定抛光时间。 晶片减薄装置还包括连接到控制器的抛光工具，该抛光工具被配置成在等于抛光时间的时间内抛光晶片。 晶片减薄装置包括连接到控制器和抛光工具的第二计量工具，并且被配置为测量抛光厚度。 控制器被配置为基于抛光厚度，预定厚度和抛光时间更新材料去除速率。