Invention Grant
US09076803B2 Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure
有权
双层成形模具的半导体装置和方法形成在积层互连结构的相对侧上
- Patent Title: Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure
- Patent Title (中): 双层成形模具的半导体装置和方法形成在积层互连结构的相对侧上
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Application No.: US14063274Application Date: 2013-10-25
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Publication No.: US09076803B2Publication Date: 2015-07-07
- Inventor: Reza A. Pagaila
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/44 ; H01L21/48 ; H01L21/50 ; H01L21/56 ; H01L21/683 ; H01L23/498 ; H01L23/538 ; H01L23/552 ; H01L25/065 ; H01L23/31 ; H01L23/00
Abstract:
A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.
Public/Granted literature
Information query
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