Invention Grant
US09082485B2 Apparatuses and methods including memory array and data line architecture
有权
包括存储器阵列和数据线架构的设备和方法
- Patent Title: Apparatuses and methods including memory array and data line architecture
- Patent Title (中): 包括存储器阵列和数据线架构的设备和方法
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Application No.: US14089337Application Date: 2013-11-25
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Publication No.: US09082485B2Publication Date: 2015-07-14
- Inventor: Toru Tanzawa
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C16/00
- IPC: G11C16/00 ; G11C16/04 ; G11C5/06 ; H01L27/105 ; H01L27/115 ; G11C16/10 ; G11C5/02
Abstract:
Some embodiments include apparatus and methods having memory cells located in different device levels of a device, at least a portion of a transistor located in a substrate of the device, and a data line coupled to the transistor and the memory cells. The data line can be located between the transistor and the memory cells. Other embodiments including additional apparatus and methods are described.
Public/Granted literature
- US20140078827A1 APPARATUSES AND METHODS INCLUDING MEMORY ARRAY AND DATA LINE ARCHITECTURE Public/Granted day:2014-03-20
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