A memory controller is provided. The memory controller may comprise a first interface configured to provide an interface for communications with a host, and a second interface configured to communicate with the host through the first interface and to provide an interface for communications with a memory. The second interface may include an emulation engine configured to generate a Direct Memory Access (DMA) setup Frame Information Structure (FIS) including ready state information for data communications with the host in response to a command transferred from the host. The second interface may include a storage engine configured to access the host to fetch a physical region descriptor (PRD) before the DMA setup FIS is received from the emulation engine.