公开(公告)号：US09304938B2

公开(公告)日：2016-04-05

申请号：US14088837

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Shim ,  Eunchan Kim

IPC: G06F12/02 ,  G06F12/10 ,  G06F13/28

CPC classification number: G06F12/1081 ,  G06F12/0238 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/7203

Abstract: A data transferring method of a storage device is provided. The method may include transferring a first data to a first outbound area, transferring the first data sent to the first outbound area to a first area of a main memory corresponding to a first address programmed by an address translation unit, transferring a second data to a second outbound area in response to an indication that the address translation unit is to be reprogrammed, and transferring the second data sent to the second outbound area to the first outbound area.

Abstract translation: 提供了一种存储装置的数据传送方法。 该方法可以包括将第一数据传送到第一出站区域，将发送到第一出站区域的第一数据传送到与由地址转换单元编程的第一地址相对应的主存储器的第一区域，将第二数据传送到 响应于要对地址转换单元重新编程的指示的第二出站区域，以及将发送到第二出站区域的第二数据传送到第一出站区域。

公开(公告)号：US09087050B2

公开(公告)日：2015-07-21

申请号：US14088909

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Shim ,  Eunchan Kim

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A memory controller is provided. The memory controller may comprise a first interface configured to provide an interface for communications with a host, and a second interface configured to communicate with the host through the first interface and to provide an interface for communications with a memory. The second interface may include an emulation engine configured to generate a Direct Memory Access (DMA) setup Frame Information Structure (FIS) including ready state information for data communications with the host in response to a command transferred from the host. The second interface may include a storage engine configured to access the host to fetch a physical region descriptor (PRD) before the DMA setup FIS is received from the emulation engine.

Abstract translation: 提供存储器控制器。 存储器控制器可以包括被配置为提供用于与主机通信的接口的第一接口和被配置为通过第一接口与主机通信并且提供用于与存储器通信的接口的第二接口。 第二接口可以包括被配置为响应于从主机传送的命令而生成包括用于与主机进行数据通信的就绪状态信息的直接存储器访问（DMA）建立帧信息结构（FIS）的仿真引擎。 第二接口可以包括被配置为在从仿真引擎接收到DMA建立FIS之前访问主机以获取物理区域描述符（PRD）的存储引擎。