In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal (CKT) goes high, (CLKZ) goes low and retention control signal is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit (D2), the clock signals (CKT) and (CLKN), the retain control signals (RET) and the control signals SS (SS) and (SSN). The signals (CKT), (CLKZ), (RET), (SS) and (SSN) determine whether the output of the clocked inverter or the second data bit (D2) is latched in the dual-port latch. Control signal (RET) determines when data is stored in the dual-port latch during retention mode.