Invention Grant
US09093555B2 Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile
有权
利用多层外延硬掩模薄膜制造改进EPI剖面的CMOS制造方法
- Patent Title: Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved EPI profile
- Patent Title (中): 利用多层外延硬掩模薄膜制造改进EPI剖面的CMOS制造方法
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Application No.: US13950842Application Date: 2013-07-25
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Publication No.: US09093555B2Publication Date: 2015-07-28
- Inventor: Deborah Jean Riley , Seung-Chul Song
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Frank D. Cimino
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.
Public/Granted literature
- US20150031177A1 METHOD OF CMOS MANUFACTURING UTILIZING MULTI-LAYER EPITAXIAL HARDMASK FILMS FOR IMPROVED EPI PROFILE Public/Granted day:2015-01-29
Information query
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