公开(公告)号：US09263444B2

公开(公告)日：2016-02-16

申请号：US14472007

申请日：2014-08-28

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean Riley ,  Judy Browder Shaw ,  Christopher L. Hinkle ,  Creighton T. Buie

IPC: H01L23/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/47 ,  H01L29/78

CPC classification number: H01L21/823871 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66643 ,  H01L29/7839 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided having a plurality of transistors formed thereon, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region on the silicon including surface. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and n-type surface regions.

Abstract translation: 制造用于集成电路（IC）的肖特基势垒触点的方法。 提供了包括含硅表面的衬底，其上形成有多个晶体管，其中多个晶体管包括至少一个暴露的p型表面区域和在包含硅的表面上的至少一个暴露的n型表面区域。 沉积包含Yb和Pt的多种金属以在基底上形成至少一个金属层。 金属层被加热以在暴露的p型和n型表面区域上形成包括硅氮化物和Ybilicide的不均匀的硅化物层。

公开(公告)号：US09780001B2

公开(公告)日：2017-10-03

申请号：US14987953

申请日：2016-01-05

Applicant: Texas Instruments Incorporated ,  Board of Regents, The University of Texas System

Inventor： Deborah Jean Riley ,  Judy Browder Shaw ,  Christopher L. Hinkle ,  Creighton T. Buie

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78 ,  H01L29/47

CPC classification number: H01L21/823871 ,  H01L21/02068 ,  H01L21/28518 ,  H01L21/28537 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66643 ,  H01L29/7839 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided. A plurality of transistors are formed on the silicon including surface in at least one PMOS region and at least one NMOS region, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region. Pre-silicide cleaning removes oxide from the exposed p-type surface regions and exposed n-type surface regions. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and exposed n-type surface regions. Unreacted metal of the metal layer is stripped.

公开(公告)号：US09224656B2

公开(公告)日：2015-12-29

申请号：US13950909

申请日：2013-07-25

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean Riley ,  Seung-Chul Song

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is carbon-containing silicon nitride formed using a hydrocarbon reagent. A second layer of the hard mask is chlorine-containing silicon nitride formed on the first layer using a chlorinated silane reagent. After SiGe epitaxial source/drain regions are formed, the hard mask is removed using a wet etch which removes the second layer at a rate at least three times faster than the first layer.

Abstract translation: 可以通过形成双层硬掩模来形成包含PMOS晶体管的集成电路。 硬掩模的第一层是使用烃试剂形成的含碳氮化硅。 硬掩模的第二层是使用氯化硅烷试剂在第一层上形成的含氯氮化硅。 在形成SiGe外延源极/漏极区之后，使用湿法蚀刻去除硬掩模，其以比第一层至少三倍的速率除去第二层。

公开(公告)号：US09093555B2

公开(公告)日：2015-07-28

申请号：US13950842

申请日：2013-07-25

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean Riley ,  Seung-Chul Song

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.

Abstract translation: 可以通过形成双层硬掩模来形成包含PMOS晶体管的集成电路。 硬掩模的第一层是使用卤化硅烷试剂形成的含卤素的氮化硅。 硬掩模的第二层是使用无卤试剂在第一层上形成的氮化硅。 在PMOS晶体管中蚀刻源极/漏极空腔之后，进行具有氢的预外延烘烤。 在形成SiGe外延源极/漏极区之后，去除硬掩模。

公开(公告)号：US09659825B2

公开(公告)日：2017-05-23

申请号：US14746106

申请日：2015-06-22

Applicant: Texas Instruments Incorporated

Inventor： Deborah Jean Riley ,  Seung-Chul Song

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864

Abstract: An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.