发明授权
US09116689B2 Power consumption reduction method of swapping high load threads with low load threads on a candidate core of a multicore processor
有权
在多核处理器的候选内核上交换具有低负载线程的高负载线程的功耗降低方法
- 专利标题: Power consumption reduction method of swapping high load threads with low load threads on a candidate core of a multicore processor
- 专利标题(中): 在多核处理器的候选内核上交换具有低负载线程的高负载线程的功耗降低方法
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申请号: US13036495申请日: 2011-02-28
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公开(公告)号: US09116689B2公开(公告)日: 2015-08-25
- 发明人: Hiroki Arai
- 申请人: Hiroki Arai
- 申请人地址: JP Tokyo
- 专利权人: NEC CORPORATION
- 当前专利权人: NEC CORPORATION
- 当前专利权人地址: JP Tokyo
- 代理机构: Sughrue Mion, PLLC
- 优先权: JP2010-047959 20100304
- 主分类号: G06F1/26
- IPC分类号: G06F1/26 ; G06F1/32
摘要:
An information processing unit includes a processing unit including a plurality of processor cores; and a power consumption reduction device configured to reduce power consumption of the processing unit. The power consumption reduction device measures the loads on threads that are running in the plurality of cores; checks the number of high load threads which are threads in a high load state and the number of low load threads which are threads in a low load state for each core, on the basis of the measuring results; selects, when there exists a core having high load threads whose number is less than a preset threshold on the number of high load threads, the core as a candidate core; and replaces the high load threads existing in the candidate core with the low load threads existing in other cores when the total number of the low load threads in a core other than the candidate core is not less than the number of the high load threads in the candidate core.
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