Invention Grant
- Patent Title: Three dimensional stacked semiconductor structure and method for manufacturing the same
- Patent Title (中): 三维堆叠半导体结构及其制造方法
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Application No.: US13652701Application Date: 2012-10-16
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Publication No.: US09136277B2Publication Date: 2015-09-15
- Inventor: Erh-Kun Lai , Yen-Hao Shih
- Applicant: Macronix International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/768 ; H01L23/522

Abstract:
A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.
Public/Granted literature
- US20140103530A1 THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2014-04-17
Information query
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