公开(公告)号：US09252156B2

公开(公告)日：2016-02-02

申请号：US14633040

申请日：2015-02-26

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Yi-Hsuan Hsiao ,  Chih-Ping Chen

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

公开(公告)号：US20150109844A1

公开(公告)日：2015-04-23

申请号：US14058328

申请日：2013-10-21

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Chih-Chang Hsieh ,  Chih-Wei Hu

IPC: H01L27/105 ,  G11C7/14 ,  G11C5/06

CPC classification number: G11C7/14 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a conductive strip. The conductive structure is disposed above the stacked structure and electrically connected to the conductive strip. The conductive structure and the conductive strip have various gap distances between corresponding points of different pairs according to a basic axis.

Abstract translation: 提供了一种集成电路及其操作方法。 集成电路包括堆叠结构和导电结构。 堆叠结构包括导电条。 导电结构设置在堆叠结构之上并电连接到导电条。 导电结构和导电条根据基本轴线在不同对的对应点之间具有不同的间隙距离。

公开(公告)号：US08987914B2

公开(公告)日：2015-03-24

申请号：US13907607

申请日：2013-05-31

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Yi-Hsuan Hsiao ,  Chih-Ping Chen

IPC: H01L23/498 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

Abstract translation: 一种形成层间导体结构的方法。 该方法包括形成耦合到用于电路的相应有源层的半导体焊盘堆叠。 半导体焊盘包括外周边，每个外围具有耦合到相应有源层的一侧。 杂质沿着外部周边植入，以形成垫上的较低电阻区域外部。 然后在半导体焊盘的堆叠中形成开口，以暴露对应的半导体焊盘上的层间导体的着陆区域，并且在至少一个半导体焊盘上限定内部周边。 通过注入用于层间导体接触的杂质并且被配置为与相应的外部较低电阻区域重叠并连续地沿着内周边形成内部较低电阻区域。

公开(公告)号：US08969202B2

公开(公告)日：2015-03-03

申请号：US14174931

申请日：2014-02-07

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Ying-Tso Chen ,  Shih-Chang Tsai ,  Chun-Fu Chen

IPC: H01L21/44 ,  H01L21/8234 ,  H01L21/302 ,  H01L21/461 ,  H01L21/283 ,  H01L27/105 ,  H01L21/28 ,  H01L29/49 ,  H01L27/118

CPC classification number: H01L21/283 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/823443 ,  H01L27/1052 ,  H01L29/4933

Abstract: A method of manufacturing a metal silicide is disclosed below. A substrate having a first region and a second region is provided. A silicon layer is formed on the substrate. A planarization process is performed to make the silicon layer having a planar surface. A part of the silicon layer is removed to form a plurality of first gates on the first region and to form a plurality of second gates on the second region. The height of the first gates is greater than the height of the second gates, and top surfaces of the first gates and the second gates have the same height level. A dielectric layer covering the first gates and the second gates is formed and exposes the top surfaces of the first gates and the second gates. A metal silicide is formed on the top surfaces of the first gates and the second gates.

Abstract translation: 以下公开了金属硅化物的制造方法。 提供具有第一区域和第二区域的衬底。 在衬底上形成硅层。 进行平面化处理以使硅层具有平坦表面。 去除硅层的一部分以在第一区域上形成多个第一栅极，并在第二区域上形成多个第二栅极。 第一栅极的高度大于第二栅极的高度，并且第一栅极和第二栅极的顶表面具有相同的高度水平。 覆盖第一栅极和第二栅极的电介质层形成并露出第一栅极和第二栅极的顶表面。 金属硅化物形成在第一栅极和第二栅极的顶表面上。

公开(公告)号：US08735969B1

公开(公告)日：2014-05-27

申请号：US13670669

申请日：2012-11-07

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih ,  Shih-Chang Tsai

IPC: H01L29/66

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L27/101 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure, comprising a plurality of conductive strips and a plurality of insulating strips, is formed on a substrate, and the conductive strips and the insulating strips are interlaced. The first conductive blocks are formed on the stacked structure. The first conductive layers and the second conductive layers are formed on two sidewalls of the stacked structure, respectively. The conductive damascene structures are formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括堆叠结构，多个第一导电块，多个第一导电层，多个第二导电层和多个导电镶嵌结构。 在衬底上形成包括多个导电条和多个绝缘条的堆叠结构，并且导电条和绝缘条交错。 第一导电块形成在堆叠结构上。 第一导电层和第二导电层分别形成在层叠结构的两个侧壁上。 导电镶嵌结构形成在堆叠结构的两侧，其中每个第一导电块经由第一导电条和每个第二导电条经由每个导电镶嵌结构电连接。

公开(公告)号：US20140103530A1

公开(公告)日：2014-04-17

申请号：US13652701

申请日：2012-10-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L27/11575 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/5226 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer. Besides the silicide, the corresponding conductive layer could, partially or completely, further comprise a conductive material connected to the conductor. The corresponding conductive layer which the contact hole extends to has higher conductivity than other conductive layers. Also, the 3D stacked semiconductor structure could be applied to a fan-out region of a 3D flash memory.

Abstract translation: 一种三维堆叠半导体结构，包括：多个氧化物层和交替布置的导电层的堆叠，至少一个与氧化物层和导电层垂直形成的接触孔，并延伸到一个导电层，形成于侧壁 形成在接触孔中并连接相应导电层的导体，并且相应的导电层包括硅化物。 硅化物可以形成在相应导电层的边缘或整个主体上。 除了硅化物之外，相应的导电层可以部分地或完全地还包括连接到导体的导电材料。 接触孔延伸的相应的导电层具有比其它导电层更高的导电性。 此外，3D堆叠半导体结构可以应用于3D闪存的扇出区域。

公开(公告)号：US09741731B2

公开(公告)日：2017-08-22

申请号：US14578566

申请日：2014-12-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih

IPC: H01L27/11578 ,  H01L27/11524 ,  H01L27/24 ,  H01L27/108 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/06 ,  H01L27/02 ,  H01L29/78 ,  H01L29/792 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11578 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/792

Abstract: A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (MOS) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of semiconductor layers arranged alternately. The MOS layer comprises a plurality of MOS structures connected to the conductive plugs respectively, and function as layer-selectors for selecting and decoding the to-be-operated layer.

公开(公告)号：US09425191B2

公开(公告)日：2016-08-23

申请号：US13965269

申请日：2013-08-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Yen-Hao Shih ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/06 ,  H01L27/115

CPC classification number: H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，3D存储器阵列，外围电路和导电连接结构。 3D存储器阵列和外围电路堆叠在基板上。 外围电路包括图案化金属层和电连接到图案化金属层的接触结构。 导电连接结构电连接到图案化的金属层。 3D存储器阵列经由导电连接结构电连接到外围电路。

公开(公告)号：US09419010B2

公开(公告)日：2016-08-16

申请号：US14488937

申请日：2014-09-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yen-Hao Shih ,  Chih-Ping Chen ,  Sheng-Chih Lai

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/768 ,  H01L27/11556

Abstract: A plurality of semiconductor layers is etched to define a first plurality of stacks of active strips between a first plurality of trenches. A first memory layer is formed on side surfaces of active strips in the first plurality of trenches, and a first layer of conductive material is formed over the first memory layer. The first plurality of stacks is etched to define a second plurality of stacks of active strips between a second plurality of trenches of the plurality of semiconductor layers. A second memory layer is formed on side surfaces of active strips in the second plurality of trenches, and a second layer of conductive material is formed over the second memory layer. Channel regions of memory cells in the memory device are formed in active strips of the plurality of semiconductor layers in the second plurality of stacks.

Abstract translation: 蚀刻多个半导体层以在第一多个沟槽之间限定活动条的第一多个堆叠。 第一存储层形成在第一多个沟槽中的活性条的侧表面上，并且第一层导电材料形成在第一存储层上。 蚀刻第一组多个叠层以在多个半导体层的第二多个沟槽之间限定有效条带的第二多个叠层。 第二存储层形成在第二多个沟槽中的活性条的侧表面上，并且第二层导电材料形成在第二存储层上。 存储器件中的存储器单元的通道区域形成在第二多个堆叠中的多个半导体层的有源条带中。

公开(公告)号：US09336867B2

公开(公告)日：2016-05-10

申请号：US14148545

申请日：2014-01-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsiang-Lan Lung ,  Ming-Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

Abstract: An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

Abstract translation: 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。