Invention Grant
- Patent Title: Reduced capacitance interlayer structures and fabrication methods
- Patent Title (中): 降低电容层间结构和制造方法
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Application No.: US14027479Application Date: 2013-09-16
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Publication No.: US09142451B2Publication Date: 2015-09-22
- Inventor: Sunil Kumar Singh , Matthew Herrick , Teck Jung Tang , Dewei Xu
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rithnberg Farley & Mesiti P.C.
- Agent Naresh K. Kannan, Esq.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/48

Abstract:
Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.
Public/Granted literature
- US20150076705A1 REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS Public/Granted day:2015-03-19
Information query
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