公开(公告)号：US09142451B2

公开(公告)日：2015-09-22

申请号：US14027479

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Matthew Herrick ,  Teck Jung Tang ,  Dewei Xu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.

Abstract translation: 提供具有降低的介电常数的层间制造方法和层间结构。 所述方法包括例如：提供具有可蒸发材料的第一未固化绝缘层; 以及在第一未固化绝缘层上设置具有致孔剂的第二未固化绝缘层。 层间结构包括第一绝缘层和第二绝缘层，并且所述方法还包括固化层间结构，在第一绝缘层中留下空气间隙，以及空气间隙大于孔的第二绝缘层中的孔，以及 其中气隙和气孔降低了层间结构的介电常数。

公开(公告)号：US20200035495A1

公开(公告)日：2020-01-30

申请号：US16045111

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dewei Xu ,  Lili Cheng ,  Shinichiro Kakita ,  Ushasree Katakamsetty ,  Roderick A. Augur

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/67 ,  B24B37/005

Abstract: Apparatus and methods of chemical-mechanical polishing of a layer on a wafer. A plurality of polishers arranged on a rotating plate, and a carrier is configured to hold the wafer and to place the layer in contact with the polishers. Each polisher includes a platen and a force-applying device operatively connected to the platen, and the force-applying device is configured to apply a variable force to the platen in order to change a rate of material removal over an area of the layer on the wafer contacted by a polishing pad carried by the platen.

公开(公告)号：US10109706B1

公开(公告)日：2018-10-23

申请号：US15643721

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Devender ,  Sunil K. Singh ,  M. Golam Faruk ,  Dewei Xu

IPC: H01L21/31 ,  H01L49/02 ,  H01L21/311 ,  H01L21/027 ,  H01L21/283 ,  H01L21/3105 ,  H01L27/12

Abstract: The present disclosure describes a method or forming vertical natural capacitor (VNCAP) and the resulting device. The method includes applying a patterned mask over an insulation layer. The method includes forming using the patterned mask, a dielectric trench in the insulation layer. The method includes depositing a high dielectric constant k (high k) layer in the dielectric trench. The method includes forming a first trench and a second trench in the high k dielectric layer. The high k dielectric layer is disposed between the first trench and the second trench. The method includes depositing metal in the first trench and the second trench.