公开(公告)号：US09171735B2

公开(公告)日：2015-10-27

申请号：US13767993

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

IPC: H01L21/308 ,  G03F7/00

CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。

公开(公告)号：US09142451B2

公开(公告)日：2015-09-22

申请号：US14027479

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Matthew Herrick ,  Teck Jung Tang ,  Dewei Xu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.

Abstract translation: 提供具有降低的介电常数的层间制造方法和层间结构。 所述方法包括例如：提供具有可蒸发材料的第一未固化绝缘层; 以及在第一未固化绝缘层上设置具有致孔剂的第二未固化绝缘层。 层间结构包括第一绝缘层和第二绝缘层，并且所述方法还包括固化层间结构，在第一绝缘层中留下空气间隙，以及空气间隙大于孔的第二绝缘层中的孔，以及 其中气隙和气孔降低了层间结构的介电常数。

公开(公告)号：US20140235055A1

公开(公告)日：2014-08-21

申请号：US13767993

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

IPC: H01L21/308

CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。