Invention Grant
- Patent Title: Predictive periodic synchronization using phase-locked loop digital ratio updates
- Patent Title (中): 使用锁相环数字比较更新的预测周期性同步
-
Application No.: US14064045Application Date: 2013-10-25
-
Publication No.: US09143315B2Publication Date: 2015-09-22
- Inventor: Mark Buckler , Sudha Thiruvengadam
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Staniford Tomita LLP
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H04L7/033

Abstract:
Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.
Public/Granted literature
- US20150117582A1 PREDICTIVE PERIODIC SYNCHRONIZATION USING PHASE-LOCKED LOOP DIGITAL RATIO UPDATES Public/Granted day:2015-04-30
Information query
IPC分类: