Invention Grant
US09143367B2 Clock and data recovery architecture with adaptive digital phase skew
有权
具有自适应数字相位偏移的时钟和数据恢复架构
- Patent Title: Clock and data recovery architecture with adaptive digital phase skew
- Patent Title (中): 具有自适应数字相位偏移的时钟和数据恢复架构
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Application No.: US13955676Application Date: 2013-07-31
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Publication No.: US09143367B2Publication Date: 2015-09-22
- Inventor: Pervez M. Aziz , Amaresh V. Malipatil , Viswanath Annampedu
- Applicant: LSI Corporation
- Applicant Address: SG
- Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Current Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
- Current Assignee Address: SG
- Agency: Sheridan Ross P.C.
- Main IPC: H04L25/03
- IPC: H04L25/03

Abstract:
In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank.
Public/Granted literature
- US20150016497A1 CLOCK AND DATA RECOVERY ARCHITECTURE WITH ADAPTIVE DIGITAL PHASE SKEW Public/Granted day:2015-01-15
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