公开(公告)号：US20150016497A1

公开(公告)日：2015-01-15

申请号：US13955676

申请日：2013-07-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Amaresh V. Malipatil ,  Viswanath Annampedu

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/0029 ,  H04L7/02 ,  H04L7/033 ,  H04L2025/03598

Abstract: In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank.

Abstract translation: 在所描述的实施例中，使用基于数字信号处理的SERDES装置来产生样本判定的方法包括：将模拟信号转换为数字信号，均衡数字信号，选择主CDR环路中的相位检测器的输入，计算相位差 信号，通过第一内插滤波器组产生对于最后均衡级的信号的相位偏移，产生控制信号以通过相位偏移适配环路来控制由第一内插滤波器组提供的相位，并且更新相位偏移值以产生 作出决定。 插入在均衡级之间的第一内插滤波器组被配置为产生到最后均衡级的相位偏移信号，并且响应于最后均衡级的相位偏移环被配置为调整由第一内插滤波器组提供的相位偏移 。

公开(公告)号：US09397674B2

公开(公告)日：2016-07-19

申请号：US14145493

申请日：2013-12-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Shiva Prasad Kotagiri ,  Sundeep Venkatraman ,  Sunil Srinivasa ,  Amaresh V. Malipatil

IPC: H03D3/24 ,  H03L7/087 ,  H03L7/06

CPC classification number: H03L7/087 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/093 ,  H04L7/0058 ,  H04L7/033

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract translation: 时钟和数据恢复装置包括相位检测器，量化器和环路滤波器。 相位检测器在表示相位调整时钟和输入数据信号之间的相位差的输出端产生相位误差采样。 量化器耦合到相位检测器的输出并响应于高阈值和低阈值，在输出端产生三值量化的相位误差样本。 环路滤波器对量化的相位误差样本或相位误差采样进行滤波，以控制相位控制时钟。 确定输入数据信号中存在的抖动频率的频率检测器寻址查找表以提供抖动频率相关的高和低阈值，并且控制环路滤波器处理哪些相位误差采样。 频率检测器通过取低通滤波相位误差样本的峰值比来确定抖动频率。

公开(公告)号：US08908816B2

公开(公告)日：2014-12-09

申请号：US13719954

申请日：2012-12-19

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Hiroshi Kimura

IPC: H03D1/04 ,  H03D1/06 ,  H03K5/01 ,  H03K6/04 ,  H04B1/10 ,  H04L1/00 ,  H04L25/08 ,  H04L25/03

CPC classification number: H04L25/03 ,  H03F1/3247 ,  H03F1/3258 ,  H03F3/195 ,  H03F2201/3212 ,  H04L25/03057 ,  H04L25/03885

Abstract: A receiver containing analog circuitry that generates distortion, a distortion compensation circuit coupled to an output of the analog circuitry, and a slicer, operating as a signal peak detector, coupled to the distortion compensation circuitry. The distortion compensation circuit has a subtractor, a function generator, and a weighting circuit. The subtractor has a first input coupled to the output of the analog circuitry, a second input, and an output. The function generator has an input coupled to the first input of the subtractor. The weighting circuit, responsive to a weighting coefficient, is coupled between an output of the function circuit and the second input of the first subtractor. The function generator has a transfer function with a third-power term and the weighting coefficient is set to a value based on the level of the signal peaks that will least partially reduce distortion in signals on the output of the subtractor.

Abstract translation: 包含产生失真的模拟电路的接收器，耦合到模拟电路的输出的失真补偿电路以及耦合到失真补偿电路的作为信号峰值检测器操作的限幅器。 失真补偿电路具有减法器，函数发生器和加权电路。 减法器具有耦合到模拟电路的输出的第一输入，第二输入和输出。 函数发生器具有耦合到减法器的第一输入的输入。 响应于加权系数的加权电路耦合在功能电路的输出和第一减法器的第二输入之间。 函数发生器具有具有第三功率项的传递函数，并且加权系数被设置为基于将最小程度地减少减法器的输出上的信号中的失真的信号峰值的电平的值。

公开(公告)号：US08860467B2

公开(公告)日：2014-10-14

申请号：US13866888

申请日：2013-04-19

Applicant: LSI Corporation

Inventor： Amaresh V. Malipatil ,  Sunil Srinivasa ,  Adam B. Healey ,  Pervez M. Aziz

IPC: G01R25/00 ,  H03L7/00

CPC classification number: H03L7/00 ,  H03L7/0807 ,  H03L7/089 ,  H03L7/091 ,  H04L7/033

Abstract: An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

Abstract translation: 一种装置包括多个相位检测器电路和一个求和电路。 多个相位检测器电路中的每一个可以被配置为响应于相应的数据样本对和中间转换样本而产生相位上升信号和相位降低信号。 求和电路可以被配置为响应于多个相位检测器电路的相位上升和下降信号而产生调整信号。 对相位相加信号和相位下降信号之和进行加权，以提供相位调整的偏置。

公开(公告)号：US20140266338A1

公开(公告)日：2014-09-18

申请号：US13866888

申请日：2013-04-19

Applicant: LSI Corporation

Inventor： Amaresh V. Malipatil ,  Sunil Srinivasa ,  Adam B. Healey ,  Pervez M. Aziz

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03L7/0807 ,  H03L7/089 ,  H03L7/091 ,  H04L7/033

Abstract: An apparatus includes a plurality of phase detector circuits and a summing circuit. Each of the plurality of phase detector circuits may be configured to generate a phase up signal and a phase down signal in response to a respective pair of data samples and intervening transition sample. The summing circuit may be configured to generate an adjustment signal in response to the phase up and phase down signals of the plurality of phase detector circuits. A sum of the phase up signals and a sum of the phase down signals are weighted to provide a bias to a phase adjustment.

Abstract translation: 一种装置包括多个相位检测器电路和一个求和电路。 多个相位检测器电路中的每一个可以被配置为响应于相应的数据样本对和中间转换样本而产生相位上升信号和相位降低信号。 求和电路可以被配置为响应于多个相位检测器电路的相位上升和下降信号而产生调整信号。 对相位相加信号和相位下降信号之和进行加权，以提供相位调整的偏置。

公开(公告)号：US09143367B2

公开(公告)日：2015-09-22

申请号：US13955676

申请日：2013-07-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Amaresh V. Malipatil ,  Viswanath Annampedu

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/0029 ,  H04L7/02 ,  H04L7/033 ,  H04L2025/03598

Abstract: In described embodiments, a method for producing sample decisions with a digital signal processing-based SERDES device includes converting an analog signal to a digital signal, equalizing the digital signal, selecting inputs for a phase detector in a main CDR loop, computing a phase difference signal, producing a phase skew to signals for a last equalization stage by a first interpolation filter bank, generating a control signal to control the phase provided by the first interpolation filter bank by a phase skew adaptation loop, and updating the phase skew values to generate a resulting decision. A device includes a first interpolation filter bank inserted between the equalization stages is configured to generate phase skew signals to a last equalization stage and a phase skew loop responsive to the last equalization stage is configured to adjust the phase skew provided by the first interpolation filter bank.

Abstract translation: 在所描述的实施例中，使用基于数字信号处理的SERDES装置来产生样本判定的方法包括：将模拟信号转换为数字信号，均衡数字信号，选择主CDR环路中的相位检测器的输入，计算相位差 信号，通过第一内插滤波器组产生对于最后均衡级的信号的相位偏移，产生控制信号以通过相位偏移适配环路来控制由第一内插滤波器组提供的相位，并且更新相位偏移值以产生 作出决定。 插入在均衡级之间的第一内插滤波器组的装置被配置为产生到最后的均衡级的相位偏移信号，并且响应于最后的均衡级的相位偏移环被配置为调整由第一内插滤波器组提供的相位偏移 。

公开(公告)号：US09106462B1

公开(公告)日：2015-08-11

申请号：US14336986

申请日：2014-07-21

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Amaresh V. Malipatil ,  Mohammad S. Mobin

IPC: H04L25/04 ,  H04L25/03

CPC classification number: H04L25/03057 ,  H04L2025/03694 ,  H04L2025/037

Abstract: Described embodiments include a process and apparatus that takes into account the operating voltage and temperature (VT) variations of a SERDES receiver implemented in an integrated circuit (IC) or system-on-chip (SoC). An analog equalizer (AEQ) adaptation loop and a decision feedback equalizer (DFE) adaptation loop are disabled after the loops have converged or stabilized the parameters of the AEQ and DFE. While the AFE and DFE adaptation loops are disabled, certain monitor coefficients related to signals corrected by the AFE and DFE are adapted and metrics derived therefrom are generated. The metrics are compared to threshold values to check if they have sufficiently changed over time to warrant re-enabling of the AFE and DFE adaptation loops.

Abstract translation: 所描述的实施例包括考虑在集成电路（IC）或片上系统（SoC）中实现的SERDES接收器的工作电压和温度（VT）变化的过程和装置。 在环路收敛或稳定AEQ和DFE的参数之后，禁用模拟均衡器（AEQ）适配环路和判决反馈均衡器（DFE）适配环路。 当AFE和DFE自适应环路被禁用时，与由AFE和DFE校正的信号有关的某些监视系数被调整，并且产生从其导出的度量。 将度量与阈值进行比较，以检查它们是否随时间发生充分变化，以保证AFE和DFE适配环路的重新启用。

公开(公告)号：US20150188551A1

公开(公告)日：2015-07-02

申请号：US14145493

申请日：2013-12-31

Applicant: LSI Corporation

Inventor： Pervez M. Aziz ,  Shiva Prasad Kotagiri ,  Sundeep Venkatraman ,  Sunil Srinivasa ,  Amaresh V. Malipatil

IPC: H03L7/087 ,  H03L7/06

CPC classification number: H03L7/087 ,  H03L7/06 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/093 ,  H04L7/0058 ,  H04L7/033

Abstract: A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples or the phase error samples to control the phase-controlled clock. A frequency detector, determining the frequency of jitter present in the input data signal, addresses a look-up table to provide the jitter-frequency dependent high and low threshold values and to control which phase error samples is processed by the loop filter. The frequency detector determines the jitter frequency by taking the ratio of peak values of low pass-filtered phase error samples.

Abstract translation: 时钟和数据恢复装置包括相位检测器，量化器和环路滤波器。 相位检测器在表示相位调整时钟和输入数据信号之间的相位差的输出端产生相位误差采样。 量化器耦合到相位检测器的输出并响应于高阈值和低阈值，在输出端产生三值量化的相位误差样本。 环路滤波器对量化的相位误差样本或相位误差采样进行滤波，以控制相位控制时钟。 确定输入数据信号中存在的抖动频率的频率检测器寻址查找表以提供抖动频率相关的高和低阈值，并且控制环路滤波器处理哪些相位误差采样。 频率检测器通过取低通滤波相位误差样本的峰值比来确定抖动频率。

公开(公告)号：US08831142B2

公开(公告)日：2014-09-09

申请号：US13717973

申请日：2012-12-18

Applicant: LSI Corporation

Inventor： Shiva Prasad Kotagiri ,  Pervez M. Aziz ,  Amaresh V. Malipatil

IPC: H04L27/00 ,  H04L27/01

CPC classification number: H04L25/063

Abstract: Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

Abstract translation: 所描述的实施例包括用于串行解串器等的接收器。 接收机具有自适应失调电压补偿能力。 偏移电压由反馈环路中的控制器取消，以根据数据判定误差信号或用于时钟恢复的定时信号产生补偿信号。

公开(公告)号：US20140211839A1

公开(公告)日：2014-07-31

申请号：US14228913

申请日：2014-03-28

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Pervez M. Aziz ,  Ye Liu

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/10 ,  H04L25/03063 ,  H04L27/0002 ,  H04L2025/03636

Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Abstract translation: 一种具有线性路径和非线性路径的接收机的通信系统。 随着接收机接收数据信号，它自适应地均衡接收信号，并且使用可饱和放大器限幅器等对非线性路径中的均衡信号进行幅度限幅。 限幅器从有限的均衡接收信号中提取数据。 在线性路径中，时钟恢复电路从均衡的接收信号产生时钟信号。 线性路径中的延迟电路至少部分地补偿限幅器中的传播延迟。 在非线性路径之外发生时钟恢复，产生低抖动时钟。 限幅器通过增加受限信号的上升和下降时间来增强数据眼睛的垂直开度，为切片机操作提供更多的噪声容限以及更大的定时裕度来采样分片数据。