Invention Grant
US09146273B2 Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device
有权
用于控制测试探针在集成在半导体和相应的电子设备上的电子设备的终端上的正确定位的过程
- Patent Title: Process for controlling the correct positioning of test probes on terminations of electronic devices integrated on a semiconductor and corresponding electronic device
- Patent Title (中): 用于控制测试探针在集成在半导体和相应的电子设备上的电子设备的终端上的正确定位的过程
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Application No.: US12974957Application Date: 2010-12-21
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Publication No.: US09146273B2Publication Date: 2015-09-29
- Inventor: Alberto Pagani
- Applicant: Alberto Pagani
- Applicant Address: IT Agrate Brianza (MB)
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza (MB)
- Agency: Gardere Wynne Sewell LLP
- Priority: ITMI09A2332 20091230
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G01R31/28
Abstract:
An embodiment for making a check of the electric type executed on wafer for testing the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on semiconductor wafer. An embodiment consists in making a current circulate in at least part of the seal ring of at least one of the above devices, and in case it has to flow in the seal ring of more devices, these seal rings are suitably interconnected to each other. Thanks to an embodiment the seal ring may also be reinforced in the angle areas of the chip, and suitable circuits may be possibly inserted in the seal ring or between the seal rings.
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